Table 3-2 – Motorola MVME2300 Series User Manual
Page 169
Functional Description
http://www.motorola.com/computer/literature
3-7
3
Notes
1. These numbers assume that the PowerPC 60x bus master is doing
address pipelining with TS_ occurring at the minimum time after
AACK_ is asserted. Also, the two numbers shown in the 1st Beat
column are for page miss/page hit.
2. In some cases, the numbers shown are averages and specific
instances may be longer or shorter.
Table 3-2. PowerPC 60
x Bus to DRAM Access Timing — 70ns Page Devices
Access Type
Clock Periods Required For:
Total
Clocks
1st
Beat
2nd
Beat
3rd
Beat
4th
Beat
4-Beat Read after Idle (Quad-
word aligned)
10
1 3
1
15
4-Beat Read after Idle (Quad-
word misaligned)
10
4
1
1
16
4-Beat Read after 4-Beat Read
(Quad-word aligned)
9/3
1
1 3
1
14/8
4-Beat Read after 4-Beat Read
(misaligned)
7/2
1
4
1
1
13/8
4-Beat Write after Idle
4
1
1
1
7
4-Beat Write after 4-Beat Write
(Quad-word aligned)
10/6
1
1
1
1
13/9
1-Beat Read after Idle
10
-
-
-
10
1-Beat Read after 1-Beat Read
11/7
1
-
-
-
11/7
1-Beat Write after Idle
4
-
-
-
4
1-Beat Write after 1-Beat Write
15/11
1
-
-
-
15/11