Motorola MVME2300 Series - Manual (Page 234)

4-10 Computer Group Literature Center Web Site
Universe (VMEbus to PCI) Chip
4
Address offsets in Table 4-2 below apply to accesses from the PCI bus and
to accesses from the VMEbus side using the VMEbus Register Access
Image (Refer to Registers in the Universe User Manual.). For register
accesses in CR/CSR space, be sure to add 508KB (0x7F00) to the address
offsets provided in the table.
Table 4-2. Universe Register Map
Offset Register Name
000 PCI Configuration Space ID Register PCI_ID
004 PCI Configuration Space Control and Status Register PCI_CSR
008 PCI Configuration Class Register PCI_CLASS
00C PCI Configuration Miscellaneous 0 Register PCI_MISC0
010 PCI Configuration Base Address Register PCI_BS
014 PCI Unimplemented
018 PCI Unimplemented
01C PCI Unimplemented
020 PCI Unimplemented
024 PCI Unimplemented
028 PCI Reserved
02C PCI Reserved
030 PCI Unimplemented
034 PCI Reserved
038 PCI Reserved
03C PCI Configuration Miscellaneous 1 Register PCI_MISC1
040 - 0FF PCI Unimplemented
100 PCI Slave Image 0 Control LSI0_CTL
104 PCI Slave Image 0 Base Address Register LSI0_BS
108 PCI Slave Image 0 Bound Address Register LSI0_BD
10C PCI Slave Image 0 Translation Offset LSI0_TO
110 Universe Reserved
114 PCI Slave Image 1 Control LSI1_CTL
118 PCI Slave Image 1 Base Address Register LSI1_BS