Motorola MVME2300 Series - Manual (Page 9)

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PCI Master .................................................................................................2-17
Generating PCI Cycles ..............................................................................2-21
Endian Conversion............................................................................................2-25
When MPC Devices are Big-Endian .........................................................2-25
When MPC Devices are Little-Endian ......................................................2-27
Raven Registers and Endian Mode............................................................2-27
Error Handling ..................................................................................................2-28
Transaction Ordering ........................................................................................2-29
Raven Registers .......................................................................................................2-30
MPC Registers ..................................................................................................2-30
Vendor ID/Device ID Registers ................................................................2-32
Revision ID Register .................................................................................2-33
General Control-Status/Feature Registers .................................................2-33
MPC Arbiter Control Register...................................................................2-36
Prescaler Adjust Register...........................................................................2-36
MPC Error Enable Register .......................................................................2-37
MPC Error Status Register ........................................................................2-39
MPC Error Address Register .....................................................................2-40
MPC Error Attribute Register - MERAT ..................................................2-41
PCI Interrupt Acknowledge Register ........................................................2-43
MPC Slave Address (0,1 and 2) Registers ................................................2-43
MPC Slave Address (3) Register...............................................................2-44
MPC Slave Offset/Attribute (0,1 and 2) Registers ....................................2-45
MPC Slave Offset/Attribute (3) Registers.................................................2-46
General-Purpose Registers ........................................................................2-47
PCI Registers ....................................................................................................2-47
Vendor ID/ Device ID Registers ...............................................................2-49
PCI Command/ Status Registers................................................................2-50
Revision ID/ Class Code Registers............................................................2-52
I/O Base Register.......................................................................................2-52
Memory Base Register ..............................................................................2-53
PCI Slave Address (0,1,2 and 3) Registers................................................2-54
PCI Slave Attribute/ Offset (0,1,2 and 3) Registers ..................................2-55
CONFIG_ADDRESS Register..................................................................2-56
CONFIG_DATA Register .........................................................................2-58
Raven Interrupt Controller .......................................................................................2-60
Features .............................................................................................................2-60
Architecture ......................................................................................................2-60
Readability of CSR ....................................................................................2-61
Interrupt Source Priority ............................................................................2-61
Processor’s Current Task Priority..............................................................2-61