Motorola MVME2300 Series - Manual (Page 268)

Glossary
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big-endian A byte-ordering method in memory where the address n of a word
corresponds to the most significant byte. In an addressed memory
word, the bytes are ordered (left to right) 0, 1, 2, 3, with 0 being the
most significant byte.
BLT BLock Transfer.
bus The pathway used to communicate between the CPU, memory, and
various input/output devices, including floppy and hard disk drives.
Available in various widths (8-, 16-, and 32-bit), with accompanying
increases in speed.
cache A high-speed memory that resides logically between a central
processing unit (CPU) and the main memory. This temporary
memory holds the data and/or instructions that the CPU is most
likely to use over and over again and avoids accessing the slower
hard or floppy disk drive.
CAS Column Address Strobe. The clock signal used in dynamic RAMs to
control the input of column addresses.
CISC Complex-Instruction-Set Computer. A computer whose processor
is designed to sequentially run variable-length instructions, many of
which require several clock cycles, that perform complex tasks and
thereby simplify programming.
CPU Central Processing Unit. The master computer unit in a system.
DCE Data Circuit-terminating Equipment.
DIMM Dual Inline Memory Module.
DMA Direct Memory Access. A method by which a device may read or
write to memory directly without processor intervention. DMA is
typically used by block I/O devices.
DRAM Dynamic Random Access Memory. A memory technology that is
characterized by extreme high density, low power, and low cost. It
must be more or less continuously refreshed to avoid loss of data.
DTE Data Terminal Equipment.
ECC Error Correction Code
EEPROM Electrically Erasable Programmable Read-Only Memory. A
memory storage device that can be written repeatedly with no
special erasure fixture. EEPROMs do not lose their contents when
they are powered down.