Motorola MVME2300 Series - Manual (Page 105)

Raven Registers
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2
MIDx Master ID. Encoded as shown below to indicate who is
currently the MPC bus master. When the internal MPC
arbiter is enabled (MARB is set), these bits are controlled
by the internal arbiter. When the internal arbiter is
disabled (MARB is clear) these bits reflect the status of
the CPUID pins. In a multi- processor environment, these
bits allow software to determine on which processor it is
currently running. The internal MPC arbiter encodes this
field as follows:
.
FEAT Feature Register. Each bit in this register reflects the
state of one of the external interrupt input pins on the
rising edge of RESET
∗
. This register may be used to
report hardware configuration parameters to system
software.
MID Current MPC Data Bus Master
00 Device on ABG0*
01 Device on ABG1*
10 Device on ABG2
11 Raven