Motorola MVME2300 Series - Manual (Page 56)

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Board Description and Memory Maps
1
General-Purpose Readable Jumpers
Headers J10 (on the MVME2300SC) and J17 (on the MVME2300)
provide eight software-readable jumpers. These jumpers can be read as a
register at ISA I/O address $801 (hexadecimal). Bit 0 is associated with
header pins 1-2; bit 7 is associated with pins 15-16. The bit values are read
as a
0 when a jumper is installed, and as a 1 when the jumper is removed.
The PowerPC firmware, PPCBug, reserves all bits, SRH0 to SRH7. The
board is shipped from the factory with J10 / J17 set to all
0 s (jumpers on
all pins), as shown in Figure 1-4.
Figure 1-4. General-Purpose Software-Readable Header
NVRAM/RTC and Watchdog Timer Registers
The M48T59/559 provides the MVME2300 series boards with 8K of non-
volatile SRAM, a time-of-day clock, and a watchdog timer. Accesses to
the M48T59/559 are accomplished via three registers:
❏ The NVRAM/RTC Address Strobe 0 register
❏ The NVRAM/RTC Address Strobe 1 register
❏ The NVRAM/RTC Data Port register
J10/J17
15
Bit 0 (SRH0)
Bit 1 (SRH1)
Bit 2 (SRH2)
Bit 6 (SRH6)
Bit 3 (SRH3)
Bit 4 (SRH4)
Bit 5 (SRH5)
1 2
16 Bit 7 (SRH7)
Reserved for future use
Reserved for future use
Reserved for future use
PPCBug INSTALLED
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use