Motorola MVME2300 Series - Manual (Page 80)

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Raven PCI Bridge ASIC
2
enabled, the MPC master will structure its bus request actions according to
the requirements of the FIFO. Use this mode with caution, since the over-
generosity of bus ownership to the MPC master can be detrimental to the
host CPU’s performance. The Bus Hog mode can be controlled by the
BHOG bit within the GCSR. The default state for BHOG is disabled.
MPC Arbiter
The MPC Arbiter is an optional feature in the Raven ASIC. It is not used
on MVME2300 series boards. Arbitration for the MPC bus on the
MVME2300 series is performed external to the Raven.
MPC Bus Timer
The MPC bus timer allows the current bus master to recover from a lock-
up condition resulting from no slave response to the transfer request.
The timeout duration of the bus timer is determined by the MBT field in
the Global Control/Status register.
The bus timer starts ticking at the beginning of an address transfer (TS
∗
asserted). If the address transfer is not terminated (AACK
∗
asserted)
before the timeout period has elapsed, the Raven will assert the MATO bit
in the MPC Error Status register, latch the MPC address in the MPC Error
Address register, and then terminate the cycle.
The MATO bit may be configured to generate an interrupt or a machine
check through the MEREN register.
The timer is disabled if the transfer is intended for PCI. PCI-bound
transfers will be timed by the PCI master.
PCI Interface
The Raven PCI interface is designed for direct connection to a PCI Local
Bus. It supports Master and Target transactions within Memory space, I/O
space, and Configuration space.