Motorola MVME2300 Series - Manual (Page 176)

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Falcon ECC Memory Controller Chip Set
3
Error Logging
ECC error logging is facilitated by the Falcon because of its internal
latches. When an error (single- or double-bit) occurs in the DRAMs to
which a Falcon is connected, it records the address and syndrome bits
associated with the data in error. Each Falcon performs this logging
function independently of the other. Once a Falcon has logged an error, it
does not log any more until the elog control /status bit has been cleared by
software unless the currently logged error is single-bit and a new, double-
bit error is encountered. The logging of errors that occur during scrub can
be enabled/disabled in software. Refer to the
Error Logger Register
section of this chapter.
DRAM Tester
The DRAM tester is for factory testing purposes only; it should not be used
by customers.
ROM/Flash Interface
The Falcon pair provides the interface for two blocks of ROM/Flash. Each
block provides addressing and control for up to 64MB. Note that no error
checking (ECC or Parity) is provided for the ROM/Flash.
The ROM/Flash interface allows each block to be individually configured
by jumpers and/or by software as follows:
1. Access for each block is controlled by two software-programmable
control register bits: an overall enable, a write enable, and a reset
vector enable. The overall enable controls normal read accesses.
The write enable is used to program Flash devices. The reset vector
enable controls whether the block is also enabled at $FFF00000 -
$FFFFFFFF. The overall enable and write enable bits are always
cleared at reset. The reset vector enable bit is cleared or set at reset
depending on external jumper configuration. This allows the board
designer to use external jumpers to enable/disable Block A/B
ROM/Flash as the source of reset vectors.
The write enable bit is cleared at reset for both blocks.