Motorola MVME2300 Series - Manual (Page 15)

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List of Figures
Figure 1-1. MVME2300 Series System Block Diagram ...........................................1-5
Figure 1-2. VMEbus Master Mapping.....................................................................1-20
Figure 1-3. VMEbus Slave Mapping .......................................................................1-22
Figure 1-4. General-Purpose Software-Readable Header........................................1-32
Figure 2-1. Raven Block Diagram .............................................................................2-3
Figure 2-2. MPC-to-PCI Address Decoding..............................................................2-5
Figure 2-3. MPC to PCI Address Translation ............................................................2-6
Figure 2-4. PCI to MPC Address Decoding ............................................................2-12
Figure 2-5. PCI to MPC Address Translation ..........................................................2-13
Figure 2-6. PCI Spread I/O Address Translation .....................................................2-22
Figure 2-7. Big- to Little-Endian Data Swap...........................................................2-26
Figure 2-8. RavenMPIC Block Diagram .................................................................2-65
Figure 3-1. Falcon Pair Used with DRAM in a System ............................................3-2
Figure 3-2. Falcon Internal Data Paths (Simplified)..................................................3-3
Figure 3-3. Overall DRAM Connections ...................................................................3-4
Figure 3-4. Data Path for Reads from the Falcon Internal CSRs.............................3-22
Figure 3-5. Data Path for Writes to the Falcon Internal CSRs.................................3-23
Figure 3-6. Memory Map for Byte Reads to CSR ...................................................3-24
Figure 3-7. Memory Map for Byte Writes to Internal Register Set
and Test SRAM ........................................................................................................3-25
Figure 3-8. Memory Map for 4-Byte Reads to CSR................................................3-26
Figure 3-9. Memory Map for 4-Byte Writes to Internal Register Set
and Test SRAM ........................................................................................................3-26
Figure 3-10. PowerPC Data to DRAM Data Correspondence.................................3-60
Figure 4-1. Architectural Diagram for the Universe..................................................4-4
Figure 4-2. UCSR Access Mechanisms .....................................................................4-9
Figure 5-1. MVME2300 Series Interrupt Architecture..............................................5-2
Figure 5-2. PIB Interrupt Handler Block Diagram ....................................................5-5
Figure 5-3. Big-Endian Mode ..................................................................................5-11
Figure 5-4. Little-Endian Mode ...............................................................................5-12