Motorola MVME2300 Series - Manual (Page 139)

Raven Interrupt Controller
http://www.motorola.com/computer/literature 2-69
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There is the possibility of a priority tie between the two processors when
resolving external interrupts. In such cases the interrupt is always
delivered to processor 0. This case is not defined in the above rule set.
MPIC Registers
The following conventions are used in the Raven register charts:
❏ R Read Only field.
❏ R/W Read/Write field.
❏ S Writing a 1 to this field sets this field.
❏ C Writing a 1 to this field clears this field.
RavenMPIC Registers
The RavenMPIC register map is shown in the following table. The Off
field is the address offset from the base address of the RavenMPIC
registers in the MPC-IO or MPC-MEMORY space. Note that this map
does not depict linear addressing. The Raven PCI-SLAVE has two
decoders for generating the RavenMPIC select. These decoders will
generate a select and acknowledge all accesses which are in a reserved
256K byte range. If the index into that 256K block does not decode a valid
RavenMPIC register address, the logic will return $00000000.
The registers are 8-, 16-, or 32-bit accessible.
Table 2-10. RavenMPIC Register Map
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1 3
0 2
9 2
8 2
7 2
6 2
5 2
4 2
3 2
2 2
1 2
0 1
9 1
8 1
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 9 8 7 6 5 4 3 2 1 0 Off
FEATURE REPORTING REGISTER 0 $01000
GLOBAL CONFIGURATION REGISTER 0 $01020
MPIC VENDOR IDENTIFICATION REGISTER $01080
PROCESSOR INIT REGISTER $01090