Motorola MVME2300 Series - Manual (Page 168)

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Falcon ECC Memory Controller Chip Set
3
the access time. Further savings come when the new address cycle is to an
address close enough to the previous one that it falls within the same row
in the DRAM array. When this happens, the Falcon pair can transfer the
data for the next cycle by cycling CAS without cycling RAS.
Single-beat Reads/Writes
Single-beat cycles to and from the PowerPC 60x bus do not achieve data
rates as high as do four-beat cycles. The Falcon pair does take advantage
of the PowerPC 60x address pipelining as much as possible for single-beat
accesses.
Single-beat writes are the slowest type of accesses because they require
that the Falcon pair perform first a read cycle, then a write cycle to the
DRAM in order to complete. When the Falcon pair can take advantage of
address pipelining, back-to-back single-beat writes take 10 clocks to
complete.
DRAM Speeds
The Falcon pair can be configured for three different DRAM speeds: 50ns,
60ns and 70ns. When the Falcon pair is configured for 50ns DRAMs, it
assumes that the devices are Hyper-Page parts. When the Falcon pair is
configured for 70ns DRAMs, it assumes that the devices are Page parts.
When the pair is configured for 60ns DRAMs, it allows the devices to be
either Page or Hyper-Page parts. Performance summaries using the
different devices are shown in
Table 3-2 , Table 3-3 , and Table 3-4 .