Motorola MVME2300 Series - Manual (Page 132)

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Raven PCI Bridge ASIC
2
Nesting of Interrupt Events
A processor is guaranteed never to have an in-service interrupt preempted
by an equal- or lower-priority source. An interrupt is considered to be in
service from the time its vector is returned during an interrupt
acknowledge cycle until an EOI is received for that interrupt. The EOI
cycle indicates the end of processing for the highest-priority in-service
interrupt.
Spurious Vector Generation
Under certain circumstances the RavenMPIC will not have a valid vector
to return to the processor during an interrupt acknowledge cycle. In these
cases, the spurious vector from the spurious vector register will be
returned. The following cases would cause a spurious vector fetch.
❏ INT is asserted in response to an externally sourced interrupt which
is activated with level sensitive logic and the asserted level is
negated before the interrupt is acknowledged.
❏ INT is asserted for an interrupt source which is masked using the
mask bit in the Vector-Priority register before the interrupt is
acknowledged.
Interprocessor Interrupts (IPI)
Processors 0 and 1 can generate interrupts which are targeted for the other
processor or both processors. There are four Interprocessor Interrupt (IPI)
channels. The interrupts are initiated by writing a bit in the IPI dispatch
registers. If subsequent IPIs are initiated before the first is acknowledged,
only one IPI will be generated. The IPI channels deliver interrupts in
Direct mode and can be directed to more than one processor.
8259 Compatibility
The RavenMPIC provides a mechanism to support PC-AT compatible
chip sets using the 8259 interrupt controller architecture. After power-on
reset, the RavenMPIC defaults to 8259 pass-through mode. In this mode,
interrupts from external source number 0 (the interrupt signal from the
8259 is connected to this external interrupt source on the RavenMPIC) are