Motorola MVME2300 Series - Manual (Page 97)

Functional Description
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When MPC Devices are Little-Endian
When all MPC devices are operating in little-endian mode, the originating
address is modified to remove the exclusive-ORing applied by MPC60x
processors before being passed on to the PCI bus. Note that no data
swapping is performed. Address modification happens to the originating
address regardless of whether the transaction originates from the PCI bus
or the MPC bus. The three low-order address bits are exclusive-ORed with
a three-bit value that depends on the length of the operand, as shown in
Table 2-6 .
Table 2-6. Address Modification for Little-Endian Transfers
Note The only legal data lengths supported in little-endian mode
are 1-, 2-, 4-, or 8-byte aligned transfers.
Since there are some difficulties with this method in dealing with
unaligned PCI-originated transfers, the Raven MPC master will break up
all unaligned PCI transfers into multiple aligned PCI transfers into
multiple aligned transfers on the MPC bus.
Raven Registers and Endian Mode
The Raven ASIC’s registers are not sensitive to changes in big-endian and
little-endian mode. With respect to the MPC bus (but not always the
address internal to the processor), the MPC registers are always
represented in big-endian mode. This means that the processor’s internal
view of the MPC registers will vary depending on the processor’s
operating mode.
Data
Length
(bytes)
Address
Modification
1 XOR with 111
2 XOR with 110
4 XOR with 100
8 No change