Motorola MVME2300 Series - Manual (Page 143)

Raven Interrupt Controller
http://www.motorola.com/computer/literature 2-73
2
Feature Reporting Register
NIRQ NUMBER OF IRQs. The number of the highest external
IRQ source supported. The IPI, Timer, and Raven
Detected Error interrupts are excluded from this count.
NCPU NUMBER OF CPUs. The number of the highest physical
CPU supported. This design supports two CPUs (CPU 0
and CPU 1).
VID VERSION ID. Version ID for this interrupt controller.
This value reports what level of the specification is
supported by this implementation. A version level of 02 is
used for the initial release of the MPIC specification.
Offset $01000
Bit 3
1 3
0 2
9 2
8 2
7 2
6 2
5 2
4 2
3 2
2 2
1 2
0 1
9 1
8 1
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 9 8 7 6 5 4 3 2 1 0
Name FEATURE REPORTING
NIRQ NCPU VID
Operation R R R R R
Reset $0 $00F $0 $01 $02