Table 3-3 – Motorola MVME2300 Series User Manual
Page 170
3-8
Computer Group Literature Center Web Site
Falcon ECC Memory Controller Chip Set
3
Table 3-3. PowerPC 60
x Bus to DRAM Access Timing — 60ns Page Devices.
Notes
1. These numbers assume that the PowerPC 60x bus master is doing
address pipelining with TS_ occurring at the minimum time after
AACK_ is asserted. Also, the two numbers shown in the 1st Beat
column are for page miss/page hit.
2. In some cases, the numbers shown are averages and specific
instances may be longer or shorter.
Access Type
Clock Periods Required For:
Total
Clocks
1st
Beat
2nd
Beat
3rd
Beat
4th
Beat
4-Beat Read after Idle (Quad-
word aligned)
9
1
2
1
13
4-Beat Read after Idle (Quad-
word misaligned)
9
3
1
1
14
4-Beat Read after 4-Beat Read
(Quad-word aligned)
7/3
1
1 2
1
11/7
4-Beat Read after 4-Beat Read
(misaligned)
6/2
1
3
1
1
11/7
4-Beat Write after Idle
4
1
1
1
7
4-Beat Write after 4-Beat Write
(Quad-word aligned)
7/3
1
1
1
1
10/6
1-Beat Read after Idle
9
-
-
-
9
1-Beat Read after 1-Beat Read
9/6
1
-
-
-
9/6
1-Beat Write after Idle
4
-
-
-
4
1-Beat Write after 1-Beat Write
13/10
1
-
-
-
13/10