Motorola MVME2300 Series User Manual
Page 278
Index
IN-4
Computer Group Literature Center Web Site
I
N
D
E
X
Memory Base register
Memory Configuration register (MEMCR)
memory maps
byte reads to CSRs (Falcon chip set)
byte writes to internal register set and
test SRAM (Falcon chip set)
default processor
four-byte reads to CSR (Falcon chip set)
four-byte writes to internal register set
and test SRAM (Falcon chip
set)
PCI PREP
processor CHRP
processor PREP
Raven PCI configuration registers
Raven PCI I/O registers
VMEbus master
VMEbus slave
MK48T59/559 access registers
module configuration and status registers
MPC
address mapping
arbiter (Raven PCI Bridge ASIC)
bus address space (Raven PCI Bridge
bus interface (Raven PCI Bridge ASIC)
bus timer (Raven PCI Bridge ASIC)
bus transfer types (Raven PCI Bridge
Error Address register
Error Attribute register (MERAT)
Error Enable register
Error Status register
master function (Raven PCI Bridge
Slave Address (0,1 and 2) registers
slave function (Raven PCI Bridge ASIC)
Slave Offset/Attribute (0,1 and 2) regis-
Slave Offset/Attribute (3) registers
write posting (Raven PCI Bridge ASIC)
MPC-to-PCI address decoding
MPC-to-PCI address translation
MPIC registers (Raven ASIC)
MVME2300 series interrupt architecture
N
negation, definition of
P
P2 signal routing
parity checking and Falcon chip set
PCI
address mapping (Raven PCI Bridge
arbitration
CHRP memory map
Command/ Status registers
configuration access
interface function (Raven PCI Bridge
interface function (Universe ASIC)
Interrupt Acknowledge register
master function (Raven PCI Bridge
memory maps
PREP memory map
registers (Raven ASIC)
reset problems with Universe ASIC
Slave Address (0,1,2 and 3) registers