Motorola MVME2300 Series - Manual (Page 107)

Raven Registers
http://www.motorola.com/computer/literature 2-37
2
MPC Error Enable Register
DFLT Default MPC Master ID. This bit determines which
MCHK
∗
pin will be asserted for error conditions in which
the MPC master ID cannot be determined or the Raven
was the MPC master. For example, in event of a PCI
parity error for a transaction in which the Raven’s PCI
master was not involved, the MPC master ID cannot be
determined. When DFLT is set, MCHK1
∗
is used. When
DFLT is clear, MCHK0
∗
is used.
MATOM MPC Address Bus Time-out Machine Check Enable.
When this bit is set, the MATO bit in the MERST register
is used to assert the MCHK output to the current address
bus master. When this bit is clear, MCHK is not asserted.
PERRM PCI Parity Error Machine Check Enable. When this
bit is set, the PERR bit in the MERST register is used to
assert the MCHK output to bus master 0. When this bit is
clear, MCHK is not asserted.
SERRM PCI System Error Machine Check Enable. When this
bit is set, the SERR bit in the MERST register is used to
assert the MCHK output to bus master 0. When this bit is
clear, MCHK is not asserted.
Address $FEFF0020
Bit
0 1 2 3 4 5 6 7 8 9
1
0 1
1 1
2 1
3 1
4 1
5 1
6 1
7 1
8 1
9 2
0 2
1 2
2 2
3 2
4 2
5 2
6 2
7 2
8 2
9 3
0 3
1
Name MEREN
DF
L
T
MA
T
O
M
PERRM SERRM SMA
M
RT
A
M
MA
T
O
II
PERRI SERRI SMA
I
RT
A
I
Operation R R
R R/W R/W R R/W R/W R/W R/W R R R/W R R/W R/W R/W R/W
Reset $00 $00
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0