Motorola MVME2300 Series - Manual (Page 175)

Functional Description
http://www.motorola.com/computer/literature 3-13
3
Error Reporting
The Falcon pair checks data from the DRAM during single- and four-beat
reads, during single-beat writes, and during scrubs.
Table 3-7 shows the
actions taken by the Falcon pair for different errors during these accesses.
Note that the Falcon pair does not assert TEA_ on double-bit errors. In fact,
the Falcon pair does not have a TEA_ signal pin and it assumes that the
system does not implement TEA_. The Falcon can, however, assert
machine check (MCP_) on double-bit errors.
Notes 1. No opportunity for error, since no read of DRAM occurs
during a four-beat write.
Table 3-7. Error Reporting
Error Type
Single-Beat/
Four-Beat Read
Single-Beat Write Four-Beat Write Scrub
Single-Bit
Error
Terminate the
PowerPC 60x bus cycle
normally.
Provide corrected data to
the PowerPC 60x bus
master.
Assert INT_ if so
enabled.
Terminate the
PowerPC 60x bus cycle
normally.
Correct the data read
from DRAM, merge with
the write data, and write
the corrected, merged
data to DRAM.
Assert INT_ if so
enabled.
N/A 1
This cycle is not seen on
the PowerPC 60x bus.
Write corrected data
back to DRAM if so
enabled.
Assert INT_ if so
enabled.
Double-Bit
Error
Terminate the
PowerPC 60x bus cycle
normally.
Provide miss-corrected,
raw DRAM data to the
PowerPC 60x bus master.
Assert INT_ if so
enabled.
Assert MCP_ if so
enabled.
Terminate the
PowerPC 60x bus cycle
normally.
Do not perform the write
portion of the read-
modify-write cycle to
DRAM.
Assert INT_ if so
enabled.
Assert MCP_ if so
enabled.
N/A 1
This cycle is not seen on
the PowerPC 60x bus.
Do not perform the
write portion of the
read-modify-write cycle
to DRAM.
Assert INT_ if so
enabled.
Triple- (or
greater)
Bit Error Some of these errors are detected correctly and are treated the same as double-bit errors. The rest could
show up as “no error” or “single-bit error”, both of which are incorrect.