Motorola MVME2300 Series - Manual (Page 180)

3-18 Computer Group Literature Center Web Site
Falcon ECC Memory Controller Chip Set
3
Refresh/Scrub
The Refresh/Scrub operation varies according to which DRAM blocks are
populated: (A and/or B) but not (C and D); or (A and/or B) and (C and/or
D).
Blocks A and/or B Present, Blocks C and D Not Present
The Falcon pair performs refreshes by doing a burst of four RAS_ cycles
approximately once every 60
µ
s. This increases to once every 30
µ
s when
certain DRAM devices are used. (The refresh rate is controlled by the
ram_fref bit in the status registers.) RAS_ is asserted to both of Blocks A
and B during each of the 4 cycles. Along with RAS_, the Falcon pair also
asserts CAS_ with (OE_ then WE_) to one of the blocks during one of the
four cycles. This forms a read-modify-write which is a scrub cycle to that
location.
After each of the 4 cycles, the DRAM row address increments by one.
When it reaches all 1s, it rolls over and starts anew at 0. Each time the row
address rolls over, the block that is scrubbed toggles between A and B.
Every second time that the row address rolls over, which of the 4 cycles
that is a scrub changes from 1st to 2nd, from 2nd to 3rd, from 3rd to 4th,
or from 4th to 1st. Every eighth time that the row address rolls over, the
column address increments by one. When the column address reaches all
ones, it rolls over and starts over at 0. Each time the column address rolls
over, the SC1, SC0 bits in the scrub/refresh register increment by 1.
$X3FFFFF9 $7FFFFF Upper
$X3FFFFFA $7FFFFF Upper
$X3FFFFFB $7FFFFF Upper
$X3FFFFFC $7FFFFF Lower
$X3FFFFFD $7FFFFF Lower
$X3FFFFFE $7FFFFF Lower
$X3FFFFFF $7FFFFF Lower
Table 3-9. PowerPC 60 x to ROM/Flash Address Mapping — ROM/Flash
64 Bits Wide (32 Bits per Falcon) (Continued)
PowerPC 60x A0-A31 ROM/Flash A22-A0 ROM/Flash Device Selected