Motorola MVME2300 Series - Manual (Page 34)

1-10 Computer Group Literature Center Web Site
Board Description and Memory Maps
1
3. Programmable via Raven ASIC.
4. CHRP requires the starting address for the PCI memory space to be
256MB-aligned.
5. Programmable via Raven ASIC for either contiguous or spread-I/O
mode.
6. The actual size of each ROM/Flash bank may vary.
7. The first Megabyte of ROM/Flash bank A appears at this range after
a reset if the rom_b_rv control bit is cleared. If the rom_b_rv control
bit is set then this address range maps to ROM/Flash bank B.
8. This range can be mapped to the VMEbus by programming the
Universe ASIC accordingly. The map shown is the recommended
setting which uses the Special PCI Slave Image and two of the four
programmable PCI Slave Images.
9. The only method of generating a PCI Interrupt Acknowledge cycle
(8259 IACK) is to perform a read access to the Raven’s PIACK
register at 0xFEFF0030.
The following table shows the programmed values for the associated
Raven MPC registers for the processor CHRP memory map.
Table 1-4. Raven MPC Register Values for CHRP Memory Map
Address Register Name Register Value
FEFF 0040 MSADD0 4000 FCFF
FEFF 0044 MSOFF0 & MSATT0 0000 00C2
FEFF 0048 MSADD1 FD00 FDFF
FEFF 004C MSOFF1 & MSATT1 0300 00C2
FEFF 0050 MSADD2 0000 0000
FEFF 0054 MSOFF2 & MSATT2 0000 0002
FEFF 0058 MSADD3 FE00 FE7F
FEFF 005C MSOFF3 & MSATT3 0200 00C0