Motorola MVME2300 Series - Manual (Page 94)

2-24 Computer Group Literature Center Web Site
Raven PCI Bridge ASIC
2
IDSEL connected to the address bit being asserted will be selected for a
configuration cycle. The Raven decodes the Device Number to determine
which of the upper address lines to assert. The decoding of the five-bit
Device Number is show below:.
The Bus Number determines which bus is the target for the configuration
read cycle. The Raven will always host PCI bus #0. Accesses that are to be
performed on the PCI bus connected to the Raven must have zero
programmed into the Bus Number. If the configuration access is targeted
for another PCI bus, then that bus number should be programmed into the
Bus Number field. The Raven will detect a nonzero field and convert the
transaction to a Type 1 Configuration cycle.
Generating PCI Special Cycles
The Raven supports the method stated in PCI Local Bus Specification 2.0
to generate special cycles using Configuration Mechanism #1. To prime
the Raven for a special cycle, the host processor must write a 32-bit value
to the CONFIG_ADDRESS register. The contents of the write are defined
later in this chapter under the CONFIG_ADDRESS register definition.
After the write to CONFIG_ADDRESS has been accomplished, the next
write to the CONFIG_DATA register causes the Raven to generate a
special cycle on the PCI bus. The write data is driven onto AD[31:0]
during the special cycle’s data phase.
Device Number Address Bit
00000 AD31
00001 - 01010 All Zeros
01011 AD11
01100 AD12
(etc.) (etc.)
11101 AD29
11110 AD30
11111 All Zeros