Document Outline

• Notification of Revisions
• Table of Contents
• List of Figures
• List of Tables
• 1 PRODUCT OVERVIEW
  • 1. OVERVIEW
  • 2. FEATURES
  • 3. BLOCK DIAGRAM
  • 4. PIN ASSIGNMENTS
  • 5. PIN DESCRIPTIONS
  • 6. MEMORY ADDRESS
• 2 A/D CONVERTER
  • 1. OVERVIEW
  • 2. BLOCK DIAGRAM
  • 3. A/D CONVERTER OPERATION
  • 4. REGISTERS DESCRIPTION
    • ADC Control Register
    • ADC Status Register
    • ADC Converter Data1 Register
    • ADC Converter Data2 Register
    • ADC Converter Data3 Register
• 3 BASIC TIMER & WATCHDOG TIMER
  • 1. OVERVIEW
  • 2. FUNCTION DESCRIPTION
    • 2.1 INTERVAL TIMER FUNCTION
    • 2.2 WATCHDOG TIMER OPERATION
    • 2.3 TIMER DURATION
    • 2.4 WATCH DOG TIMER DURATION
  • 3. REGISTERS DESCRIPTION
    • Basic Timer Control Register
    • Basic Timer Count Register
• 4 ENCODER COUNTER
  • 1. OVERVIEW
  • 2. FUNCTION DESCRIPTION
  • 3. REGISTERS DESCRIPTION
    • Encoder Counter Control Register 0
    • Encoder Counter Status Register
    • 16 Bit Position Counter Register
    • 16 Bit Position Reference Register
    • 16 Bit Speed Counter Register
    • 16 Bit Speed Reference Register
    • 16 Bit Phase A Capture Counter Register
    • 16 Bit Phase A Capture Data Register
    • 16 Bit t Phase B Capture Counter Register
    • 16 Bit Phase B Capture Data Register
• 5 INTERNAL FLASH ROM
  • 1. OVERVIEW
  • 2. BLOCK DIAGRAM
  • 3. FLASH CONFIGURATION
    • 3.1 FLASH ROM CONFIGURATION
    • 3.2 ADDRESS ALIGNMENT
    • 3.3 WORKING MODE
    • 3.4 PROGRAM MODE
  • 4. PROGRAMMING MODES
    • 4.1 USER PROGRAM MODE
    • 4.2 NORMAL PROGRAM
    • 4.3 OPTION PROGRAM
    • 4.4 SECTOR ERASE
    • 4.5 CHIP ERASE FLOWCHART
    • 4.6 TOOL PROGRAM MODE
  • 5. DATA PROTECTION
    • 5.1 PROTECTION OPTION CONFIGURATION
    • 5.2 JTAG INTERFACE PROTECTION BIT 8
    • 5.3 HARDWARE PROTECTION BIT 17
    • 5.4 READ PROTECTION BIT 27
  • 6. REGISTERS DESCRIPTION
    • Flash Memory Key Register
    • Flash Memory Address Register
    • Flash Memory Data Register
    • Flash Memory Control Register
    • Smart Option Bits Read Register
    • Protection Option Bits Read Register
• 6 INVERTER MOTOR CONTROLLER (IMC)
  • 1. OVERVIEW
  • 2. BLOCK DIAGRAM
  • 3. FUNCTION DESCRIPTION
    • 3.1 TRI-ANGULAR WAVE
    • 3.2 SAW-TOOTH WAVE
  • 4. PHASE SIGNAL GENERATION
    • 4.1 TRI-ANGULAR WAVE (IMMODE = 0)
    • 4.2 TRI-ANGULAR WAVE (IMMODE = 0)
    • 4.3 TRI-ANGULAR WAVE (IMMODE = 0)
    • 4.4 TRI-ANGULAR WAVE (IMMODE = 0)
    • 4.5 TRI-ANGULAR WAVE (IMMODE = 0)
    • 4.6 TRI-ANGULAR WAVE (IMMODE = 0)
    • 4.7 TRI-ANGULAR WAVE (IMMODE = 0)
    • 4.8 TRI-ANGULAR WAVE (IMMODE = 0)
    • 4.9 SAW-TOOTH WAVE (IMMODE = 1)
    • 4.10 SAW-TOOTH WAVE (IMMODE = 1)
    • 4.11 SAW-TOOTH WAVE (IMMODE = 1)
    • 4.12 SAW-TOOTH WAVE (IMMODE = 1)
    • 4.13 SAW-TOOTH WAVE (IMMODE = 1)
    • 4.14 SAW-TOOTH WAVE (IMMODE = 1)
    • 4.15 SAW-TOOTH WAVE (IMMODE = 1)
    • 4.16 SAW-TOOTH WAVE (IMMODE = 1)
  • 5. REGISTERS DESCRIPTION
    • Inverter Motor Control Register 0
    • Inverter Motor Control Register 1
    • Inverter Motor Status Register
    • ADC Start Signal Select Register
    • 16-Bit Inverter Motor Counter Register
    • 16-Bit Top Compare Register
    • 16-Bit Phase A Compare Register of Rising
    • 16-Bit Phase A Compare Register of Falling
    • 16-Bit Phase B Compare Register of Rising
    • 16-Bit Phase B Compare Register of Falling
    • 16-Bit Phase C Compare Register of Rising
    • 16-Bit Phase C Compare Register of Falling
    • 16-Bit ADC Start Compare Register of Rising 0
    • 16-Bit ADC Start Compare Register of Falling 0
    • 16-Bit ADC Start Compare Register of Rising 1
    • 16-Bit ADC Start Compare Register of Falling 1
    • 16-Bit ADC Start Compare Register of Rising 2
    • 16-Bit ADC Start Compare Register of Falling 2
    • 16-Bit Dead-time Compare Register
• 7 INTERRUPT CONTROLLER
  • 1. OVERVIEW
  • 2. FUNCTIONAL DESCRIPTION
    • 2.1 CONFIGURING IRQ AND FIQ INTERRUPT SERVICE
    • 2.2 INTERRUPT REGISTERS
    • 2.3 INTERRUPT SOURCES
  • 3. REGISTERS DESCRIPTION
    • INTERRUPT MODE0 Register
    • INTERRUPT MODE1 Register
    • INTERRUPT MODE2 Register
    • INTERRUPT PENDING0 Register
    • INTERRUPT PENDING1 Register
    • INTERRUPT PENDING2 Register
    • INTERRUPT MASK0 Register
    • INTERRUPT MASK1 Register
    • INTERRUPT MASK 2 Register
    • INTERRUPT OFFSET Register for IRQ
    • INTERRUPT OFFSET Register for FIQ
    • INTERRUPT VECTOR ADDRESS Register for IRQ
    • INTERRUPT VECTOR ADDRESS Register for FIQ
    • INTERRUPT VECTOR BASE ADDRESS Register
    • INTERRUPT CONTROL Register
    • INTERRUPT PRIORITY Register
    • SOFTWARE INTERRUPT Register
• 8 I/O PORTS
  • 1. OVERVIEW
  • 2. S3F401F PORT CONFIGURATION OVERVIEW
  • 3. I/O PORT CONTROL REGISTERS
  • 4. REGISTERS DESCRIPTION
    • PORT0 Control Register
    • PORT0 Control Register
    • PORT1 Control Register
    • PORT1 Control Register
    • PORT2 Control Register
    • PORT0 Pull-Up Control Register
    • PORT1 Pull-Up Control Register
    • PORT2 Pull-Up Control Register
    • PORT0 Open-Drain Control Register
    • PORT1 Open-Drain Control Register
    • PORT2 Open-Drain Control Register
    • PORT0 Data Set Register
    • PORT0 Data Reset Register
    • PORT0 Data Status Register
    • PORT1 Data Set Register
    • PORT1 Data Reset Register
    • PORT1 Data Status Register
    • PORT2 Data Set Register
    • PORT2 Data Reset Register
    • PORT2 Data Status Register
    • External Interrupt Control Register
    • External Interrupt Control Register
    • External Interrupt Filter Control Register
    • External Interrupt Filter Control Register
• 9 CLOCK & POWER MANAGEMENT
  • 1. OVERVIEW
  • 2. PHASE LOCKED LOOP
    • 2.1 PLL
    • 2.2 PLL VALUE CHANGE STEPS
    • 2.3 CAPACITOR FOR PLL LOOP FILTER
  • 3. MODE CHANGE
  • 4. REGISTERS DESCRIPTION
    • System Control Register
    • PLL Control Register
    • PLL Locking Timer Register
    • Power Management Status Register
• 10 SSP (SYNCHRONOUS SERIAL PORT)
  • 1. OVERVIEW
    • 1.1 FEATURES
    • 1.2 PROGRAMMABLE PARAMETERS
  • 2. BLOCK DIAGRAM
    • 2.1 SSP FUNCTIONAL DESCRIPTION
    • 2.2 FRAME FORMAT
    • 2.3 INTERRUPT
  • 3. REGISTERS DESCRIPTION
    • Control Register 0
    • Control Register 1
    • Data Register
    • Status Register
    • Clock Prescale Register
    • Interrupt Mask Set /Clear Register
    • Raw Interrupt Status Register
    • Masked Interrupt Status Register
    • Interrupt Clear Register
• 11 16-BIT TIMERS
  • 1. OVERVIEW
  • 2. OPERATION DESCRIPTION
    • 2.1 INTERVAL MODE OPERATION
    • 2.2 MATCH & OVERFLOW MODE OPERATION
    • 2.3 CAPTURE MODE OPERATION
    • 2.4 PWM MODE OPERATION
  • 3. REGISTERS DESCRIPTION
    • Timer Control Register
    • Timer Pre-Scale Register
    • Timer Data Register
    • Timer Data Register for PWM
    • Timer Count Register
• 12 UART
  • 1. OVERVIEW
    • 1.1 THE UART PERFORMS:
    • 1.2 IrDA SIR BLOCK
    • 1.3 FEATURES
    • 1.4 PROGRAMMABLE PARAMETERS
    • 1.5 VARIATIONS FROM THE 16C550 UART
  • 2. BLOCK DIAGRAM
  • 3. FUNCTION DESCRIPTION
    • 3.1 BAUD RATE GENERATOR
    • 3.2 TRANSMIT FIFO
    • 3.3 TRANSMIT LOGIC
    • 3.4 RECEIVE FIFO
    • 3.5 RECEIVE LOGIC
    • 3.6 UART OPERATION
    • 3.7 IrDA SIR OPERATION
    • 3.8 INTERRUPTS
  • 4. REGISTERS DESCRIPTION
    • UART Data Register
    • Receive Status/Error Clear Register
    • UART Flag Register
    • UART IrDA Low Counter Register
    • UART Integer Baud Rate Register
    • UART Functional Baud Rate Register
    • UART Line Control Clock Register
    • UART Control Register
    • UART Interrupt FIFO Level Select Register
    • UART Interrupt Mask Set/Clear Register
    • UART Raw Interrupt Status Register
    • UART Masked Interrupt Status Register
    • UART Interrupt Clear Register
• 13 ELECTRICAL DATA
  • Table 13-1. Absolute Maximum Ratings
  • Table 13-2. D.C. Electrical Characteristics
  • Table 13-3. Timing Constants
  • Table 13-4. PLL Timing Constants
  • Table 13-5. Internal RC Oscillation Characteristics
  • Table 13-6. AC Electrical Characteristics
  • Table 13-7. 12-bit ADC Electrical Characteristics
  • Table 13-8. AC Electrical Characteristics for Internal Flash ROM
• 14 MECHANICAL DATA
  • Figure 14-1. 100-QFP-1420 Package Dimensions