Summary of automatic clock switchover feature – Altera ALTPLL (Phase-Locked Loop) IP Core User Manual
Page 16
Summary of Automatic Clock Switchover Feature
The following table summarizes automatic clock switchover support in the supported device families. Also
supports automatic clock switchover feature with manual override control.
Table 7: Automatic Clock Switchover Feature Support
Cyclone Series PLL
Fast PLL
Enhanced PLL
Left_Right
Top_Bottom
Device Family
—
No
Yes
—
—
Arria GX
—
—
—
Yes
—
Arria II GX
—
—
—
Yes
Yes
Stratix IV
—
—
—
Yes
Yes
Stratix III
—
No
Yes
—
—
Stratix II
—
No
Yes
—
—
Stratix II GX
—
No
Yes
—
—
Stratix
—
No
Yes
—
—
Stratix GX
Yes
—
—
—
—
Cyclone IV
Yes
—
—
—
—
Cyclone III
No
—
—
—
—
Cyclone II
No
—
—
—
—
Cyclone
The following table summarizes the manual clock switchover support in the supported device families.
Table 8: Manual Clock Switchover Feature Support
Cyclone Series PLL
Fast PLL
Enhanced PLL
Left_Right
Top_Bottom
Device
—
Yes
Yes
—
—
Arria GX
—
—
—
Yes
—
Arria II GX
—
—
—
Yes
Yes
Stratix IV
—
—
—
Yes
Yes
Stratix III
—
Yes
Yes
—
—
Stratix II
—
Yes
Yes
—
—
Stratix II GX
—
No
Yes
—
—
Stratix
—
No
Yes
—
—
Stratix GX
Yes
—
—
—
—
Cyclone IV
ALTPLL (Phase-Locked Loop) IP Core User Guide
Altera Corporation
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Summary of Automatic Clock Switchover Feature
16
2014.08.18