Altera ALTPLL (Phase-Locked Loop) IP Core - Manual (Page 47)

Description Type Parameter
Specifies the initial value for the corresponding counter,
C[9..0] . If omitted, default is 1 . Counters C[9..5] are
not available in Cyclone III devices onwards.
Integer
C[]_INITIAL
Specifies the value of the low period count for the
corresponding counter,
C[9..0].
If omitted, default is
1
.
Counters C[9..5] are not available in Cyclone III devices
onwards.
Integer C[]_LOW
Specifies the operation mode for the counter,
C[9..0]
.
The values are BYPASS , ODD , or EVEN . If omitted, the default
is BYPASS . Counters C[9..5] are not available in Cyclone
III devices onwards.
String
C[]_MODE
Specifies the phase tap for the counter, C[9..0] . If omitted,
default is
0
. Counters
C[9..5]
are not available in Cyclone
III devices onwards.
Integer C[]_PH
Specifies the test source for the counter, C[9..0] . If
omitted, default is
0
. Counters
C[9..5]
are not available
in Cyclone III devices onwards.
Integer C[]_TEST_SOURCE
Specifies whether to use cascade input for the counter,
C[9..1]
. Values are
ON
or
OFF
. If omitted, default is
OFF
.
Counters C[9..5] are not available in Cyclone III devices
onwards.
String C[]_USE_CASC_IN
Specifies the value of the charge pump current in
microamperes (mA). Integer
CHARGE_PUMP_CURRENT
Specifies the counter for the corresponding output clock
port,
CLK[9..0]
. Values are
UNUSED
,
C0
,
C1
,
C2
,
C3
,
C4
,
C5
,
C6
,
C7
,
C8
or
C9
. If omitted, the default is
C0
. This parameter
is not available for Cyclone II and Stratix II devices.
Counters
CLK[9..5]_COUNTER
are not available for Cyclone
III devices onwards.
String CLK[]_COUNTER
Specifies the integer division factor for the VCO frequency
of the corresponding output clock port,
CLK[9..0]
port.
The parameter value must be greater than
0
. Specify this
parameter only if the corresponding CLK[9..0] port is
used; however, it is not required if a Clock Settings
assignment is specified for the corresponding
CLK[9..0]
port. If omitted, the default is 0 . Parameters CLK[9..5]_
DIVIDE_BY
are not available in Cyclone III devices.
Integer
CLK[]_DIVIDE_BY
Specifies the duty cycle in percentage for the corresponding
output clock port,
clk[9..0] . If omitted, the default is 50 .
Parameters
CLK[9..5]_DUTY_CYCLE
are not available in
Cyclone III devices.
Integer
CLK[]_DUTY_CYCLE
Altera Corporation ALTPLL (Phase-Locked Loop) IP Core User Guide
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47 ALTPLL Parameters
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2014.08.18