Altera ALTPLL (Phase-Locked Loop) IP Core - Manual (Page 34)

Figure 25: Simulation in Quartus II Design Flow
Post-fit timing
simulation netlist
Post-fit timing
simulation (3)
Post-fit functional
simulation netlist
Post-fit functional
simulation
Analysis & Synthesis
Fitter
(place-and-route)
TimeQuest Timing Analyzer
Device Programmer
Quartus II
Design Flow
Gate-Level Simulation
Post-synthesis
functional
simulation
Post-synthesis functional
simulation netlist
(Optional) Post-fit
timing simulation
RTL Simulation
Design Entry
(HDL, Qsys, DSP Builder)
Altera Simulation
Models
EDA
Netlist
Writer
Post-fit timing simulation is not supported for 28nm and later device archetectures. Altera IP supports
a variety of simulation models, including simulation-specific IP functional simulation models and Note:
encrypted RTL models, and plain text RTL models. These are all cycle-accurate models. The models
support fast functional simulation of your IP core instance using industry-standard VHDL or Verilog
HDL simulators. For some cores, only the plain text RTL model is generated, and you can simulate
that model. Use the simulation models only for simulation and not for synthesis or any other purposes.
Using these models for synthesis creates a nonfunctional design.
Related Information
Simulating Altera Designs
Upgrading IP Cores
IP core variants generated with a previous version of the Quartus II software may require upgrading before
use in the current version of the Quartus II software. Click Project > Upgrade IP Components to identify
and upgrade IP core variants.
The Upgrade IP Components dialog box provides instructions when IP upgrade is required, optional, or
unsupported for specific IP cores in your design. You must upgrade IP cores that require it before you can
compile the IP variation in the current version of the Quartus II software. Many Altera IP cores support
automatic upgrade.
The upgrade process renames and preserves the existing variation file ( .v , . sv , or .vhd ) as <my_variant> _
BAK.v , .sv , .vhd in the project directory.
ALTPLL (Phase-Locked Loop) IP Core User Guide Altera Corporation
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Upgrading IP Cores 34
2014.08.18