Altera ALTPLL (Phase-Locked Loop) IP Core - Manual (Page 65)

Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks
To generate 133-MHz, 200-MHz, and 200-MHz time-shifted clocks, follow these steps:
Before you begin
Download and unzip the shift_clk.zip .
1. In the Quartus II software, open the project file shift_clk.qpf.
2. Open the top-level shift_clk.qpf file. You complete this project in this example.
3. Expand the I/O folder and click ALTPLL.
4. In Which type of output file do you want to create?, select AHDL.
5. For What name do you want for the output file?, name the output file as shift_pll.
6. Click Next. Page 3 appears.
7. To specify the 100 MHz input clock (
inclk0 ), perform the following steps:
8. On page 3 of the General section, for What is the frequency of the inclock0 input?, type 100 , and select
MHz.
9. Under PLL type, click Select the PLL type automatically.
10. In the Operation mode section, select In Normal Mode.
11. For Which output clock will be compensated for?, select c0.
12. Click Next. Page 4 appears.
13. In the Dynamic configuration section, turn off the Create optional inputs for dynamic reconfiguration
option.
14. In the Optional inputs section, perform the following steps:
a. Turn off Create an ‘pllena’ input to selectively enable the PLL.
b. Turn off Create an ‘areset’ input to asynchronously reset the PLL.
c. Turn off Create an ‘pfdena’ input to selectively enable the phase/frequency detector.
15. In the Lock output section, turn on Create ‘locked’ output.
16. Leave the other options in the Parameter Settings tab as the default.
17. To specify the 133 MHz output clock (
c0 ), perform the following steps:
18. Click the Output Clocks tab to see the output clocks of the PLL. Page 7 appears.
19. On the clk c0 page, turn on Use this clock.
20. In the Clock Tap Settings section, perform the following steps:
a. Turn off Enter output clock frequency.
b. Turn on Enter output clock parameters.
c. For Clock multiplication factor, type
4 .
d. For Clock division factor, type 3 .
e. For Clock phase shift, type 0 and select deg.
f. For Clock duty cycle (%), type 50.00 .
21. Leave the other options at their default values.
22. Click Next. Page 8 appears.
23. To specify the 200 MHz output clock (
c1
), perform the following steps:
24. On the clk c1 page, turn on Use this clock.
25. In the Clock Tap Settings section, perform the following steps:
a. Turn off Enter output clock frequency.
b. Turn on Enter output clock parameters.
Altera Corporation ALTPLL (Phase-Locked Loop) IP Core User Guide
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65 Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks
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2014.08.18