Altera ALTPLL (Phase-Locked Loop) IP Core - Manual (Page 43)

Description Condition Port Name
(7)
The port that feeds the
fbin
port
through the mimic circuitry. If a
feedback path is not connected,
the compiler automatically
connects the
fbout port directly
to the
fbin
port. Additionally, a
clkbuf
primitive is added to
specify the resource type used,
similarly to other clock networks.
The
fbout
port is available only if
the PLL is in external feedback
mode.
For Stratix III and Stratix IV
device families, if the PLL operates
in zero-delay buffer mode, and the
fbmimicbidir
port is not used,
you must perform the following
steps:
1. Replace the brackets,
[]
, in the
port name with an integer to
get the exact name (for
example,
c0
,
c1
,
c3
,
e0
,
e1
,
e2
,
enable1
and
sclkout0
).
2. Instantiate an ALT_IOBUF IP
core.
3. Connect the fbout and fbin
ports to the
o
and
i
ports of the
ALT_IOBUF instantiation,
respectively.
4. Connect the bidirectional port
of the ALT_IOBUF instantia-
tion to a bidirectional pin, and
set the
oe
port of the ALT_
IOBUF instantiation to 1.
Optional
fbout
(7) Replace the brackets, [] , in the port name with an integer to get the exact name (for example, c0 , c1 , c3 , e0 ,
e1
,
e2
,
enable1
and
sclkout0
).
Altera Corporation ALTPLL (Phase-Locked Loop) IP Core User Guide
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43 ALTPLL Output Ports
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2014.08.18