Altera ALTPLL (Phase-Locked Loop) IP Core User Manual
Page 7
To extract valid parameter values to maximize your PLL lock range, perform the following steps:
1. In the schematic editor, double-click the ALTPLL instance in your design to open the ALTPLL parameter
editor.
2. For What is the frequency of your inclock0 input?, type the value of the low end of your desired PLL
lock range. For example, if your application requires a lock range of 50 MHz to 100 MHz, type
50
MHz.
3. Turn on Create output file(s) using the 'Advanced' PLL parameters.
4. Turn on Create an 'inclk1' for a second inclk and enter the high end of your lock range as the frequency
for
inclk1
. For example, if your application requires a lock range of 50 MHz to 100 MHz, type
100
MHz.
5. Complete the remaining pages in the ALTPLL parameter editor.
6. Compile your project and note the lock range shown in the PLL Summary report. If it is satisfactory, note
all of the values for the PLL from this report, such as the M value, N value, charge pump current, loop
filter resistance, and loop filter capacitance.
7. In the schematic editor, double-click the ALTPLL instance in your design to open the ALTPLL parameter
editor.
8. Turn off Create an 'inclk1' for a second inclk.
9. Click Finish to update the PLL wrapper file.
10. In a text editor, open the PLL wrapper file. If the wrapper file is in Verilog format, go to the defparam
section. If the wrapper file is in VHDL HDL, go to the generic map section. Modify all of the values for
the parameters listed in step 6. Save the changes.
11. Compile your project.
12. Check the PLL Summary report to confirm the PLL lock range meets your requirements. The modified
PLL should have the desired lock range.
If your input clock frequency is too close to the end of the desired PLL lock range—for example the low end
of the desired lock range is 50 MHz and the input clock frequency is 50 MHz, the PLL might not maintain
lock when the input clock has jitter or the frequency drifts below 50 MHz. You may choose to expand your
PLL lock range to ensure your expected input clock frequency is further from the end of the range. For this
example, you can enter 45 MHz and 105 MHz to ensure that your target lock range of 50 MHz to 100 MHz
is within the PLL lock range.
The Quartus II software prompts an error message if it is unable to implement your preferred lock range
using this procedure. Therefore, you have to look into other options, such as PLL reconfiguration to support
your input frequency range.
Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing
The ALTLVDS IP core provides SERDES transmitter and receiver functionality commonly used in LVDS
interfacing.
The following table lists the options and values to configure a PLL on a Stratix III or Stratix IV device to
clock an ALTLVDS IP core.
Table 5: Options to Configure a PLL on a Stratix III or Stratix IV Device
Value
Option
Left_Right PLL
Which PLL type will you be
using?
In Source-Synchronous Compensation mode
How will the PLL outputs be
generated?
Altera Corporation
ALTPLL (Phase-Locked Loop) IP Core User Guide
7
Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing
ug-altpll
2014.08.18