Altera ALTPLL (Phase-Locked Loop) IP Core - Manual (Page 66)

c. For Clock multiplication factor, type 2 .
d. For Clock division factor, type 1 .
e. For Clock phase shift, type 0.00 and select ns.
f. For Clock duty cycle (%), type 50.00 .
26. Leave all other options at their default values.
27. Click Next. Page 9 appears.
28. To specify the 200 MHz output clock
c2 with a 1.00 nanosecond delay, perform the following steps:
29. On the clk c2 page, turn on Use this clock.
30. In the Clock Tap Settings section, perform the following steps:
a. Turn off Enter output clock frequency.
b. Turn on Enter output clock parameters.
c. For Clock multiplication factor, type
2 .
d. For Clock division factor, type 1 .
e. For Clock phase shift, type 1.00 and select deg.
f. For Clock duty cycle (%), type 50.00 .
31. Leave all other options at their default values.
32. Click Finish. Page 18 appears.
33. On page 18, ensure that the Text Design File (.tdf), Pin Planner File (.ppf), AHDL Include file (.inc),
Block Symbol File (.bsf), and Sample waveforms in summary file (.html and .jpg) are turned on.
34. Click Finish. The shift_pll module is built.
35. In the Symbol dialog box, click OK.
36. Move the pointer to place the shift_pll symbol between the input and output ports in the shift_clk.bdf.
Click to place the symbol. You have now completed the design file.
37. On the File menu, click Save Project to save the design.
The following figure shows the completed design file.
ALTPLL (Phase-Locked Loop) IP Core User Guide Altera Corporation
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Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks 66
2014.08.18