Altera ALTPLL (Phase-Locked Loop) IP Core - Manual (Page 50)

Description Type Parameter
Specifies the external counter for the corresponding
external clock output port,
EXTCLK[3..0] . Values are E0 ,
E1
,
E2
, or
E3
. If omitted, the default is
E0
. This parameter
is only available for Stratix, Stratix GX, and Cyclone
(
EXTCLK0
) devices.
String
EXTCLK[]_COUNTER
Specifies the integer division factor for the corresponding
external clock output port,
EXTCLK[3..0] , with respect to
the input clock frequency. The parameter value must be
greater than
0 . You can specify this parameter only if the
corresponding
EXTCLK[3..0]
port is used; however, it is
not required if a Clock Settings assignment is specified for
the corresponding
EXTCLK[3..0]
port. If omitted, the
default is
1
. This parameter is not available for Stratix II
devices.
Integer
EXTCLK[]_DIVIDE_BY
Specifies the duty cycle in percentage for the corresponding
external clock output port,
EXTCLK[3..0 ]. If omitted, the
default is
50
. This parameter is not available for Stratix II
devices.
Integer
EXTCLK[]_DUTY_CYCLE
Specifies the integer multiplication factor for the
corresponding external clock output port,
EXTCLK[3..0] ,
with respect to the input clock frequency. The parameter
value must be greater than 0. You can specify this
parameter only if you use the corresponding
EXTCLK[3..0]
port. However, it is not required if a Clock Settings
assignment is specified for the corresponding
EXTCLK[3..0]
port. If omitted, the default is
1
. This
parameter is not available for Stratix II devices.
Integer EXTCLK[]_MULTIPLY_BY
Specifies the phase shift for the corresponding external
clock output port,
EXTCLK[3..0]
. This parameter is not
available for Stratix II devices.
String EXTCLK[]_PHASE_SHIFT
Specifies, in picoseconds (ps), a delay value to be applied
to the corresponding external clock output port,
EXTCLK[3..0] . This parameter affects only the
corresponding EXTCLK[3..0] port and is independent of
the
EXTCLK[3..0]_PHASE_SHIFT
parameter; therefore you
can use both parameters simultaneously. If no units are
specified, picoseconds (ps) are assumed.
Legal values range from
–3
ns to
6
ns in increments of
0.25
ns. Do not use these values as parameters except when
reprogramming the PLL using the real-time programming
interface. This parameter is not available for Stratix II
devices.
String
EXTCLK[]_TIME_DELAY
ALTPLL (Phase-Locked Loop) IP Core User Guide Altera Corporation
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ALTPLL Parameters 50
2014.08.18