Altera ALTPLL (Phase-Locked Loop) IP Core - Manual (Page 62)

• ddr-clk-msim.zip
• shift_clk.zip
• shift_clk_msim.zip
Design Example 1: Differential Clock
This design example uses the ALTPLL IP core to generate an external differential clock from an enhanced
PLL. You must generate or modify clock signals to meet design specifications. When you interface to double
data rate (DDR) memory, you must generate a differential SSTL clock signal for the external device. A DDR
DIMM requires three pairs of differential SSTL clocks. You can use enhanced PLLs in Stratix devices to
generate these clock signals.
In this example, perform the following activities:
• Generate a 166-MHz differential SSTL external clock ( ddr_clk ) output from a 33.33-MHz input clock
using the ALTPLL IP core and the parameter editor.
• Implement the
DDR_CLK
design by assigning the EP1S10F780 device to the project and compiling the
project.
• Simulate the DDR_CLK design.
Generating a 166-MHz Differential SSTL External Clock
To generate a 166-MHz Differential SSTL external clock, follow these steps:
Before you begin
Download and unzip the ddr_clk.zip .
1. In the Quartus II software, open the project file \ddr_clk\ddr_clk.qpf.
2. Open the top-level \ddr_clk\ddr_clk.bdf file. You will complete this project in this example.
3. Click Tools > IP Catalog. Then expand the I/O folder and select ALTPLL
4. In Which type of output file do you want to create?, select AHDL.
5. For What name do you want for the output file?, name the output file ddr_pll.
6. For What is the frequency of the inclock0 input?, type
33.33 , and select MHz.
7. Under PLL type, click Select the PLL type automatically.
8. Under Operation mode, select Create an 'fbin' input for an external feedback (External Feedback
Mode).
9. Under Operation mode, for Which output clock will have a board level connection?, select e0 from
the drop-down menu.
10. In the Dynamic configuration section, turn off Create optional inputs for dynamic reconfiguration.
11. In the Optional inputs sections:
a. Turn on Create an ‘pllena’ input to selectively enable the PLL.
b. Turn on Create an ‘areset’ input to asynchronously reset the PLL.
c. Turn off Create an ‘pfdena’ input to selectively enable the phase/frequency detector.
12. In the Lock output section, turn on Create ‘locked’ output.
13. Leave the remaining options at their default settings.
14. Click the Output Clocks tab.
15. Click extclk e0.
ALTPLL (Phase-Locked Loop) IP Core User Guide Altera Corporation
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Design Example 1: Differential Clock 62
2014.08.18