Altera ALTPLL (Phase-Locked Loop) IP Core - Manual (Page 21)

you to configure the characteristics of the PLL loop filter. Most loop filters contain only passive components,
such as resistors and capacitors, which consumes board space. Altera FPGAs already contain these
components, and by using the programmable bandwidth feature, you can control how the components affect
the PLL bandwidth. This includes controlling the charge pump current, loop filter resistance, and high
frequency capacitance values. The charge pump current affects the PLL bandwidth directly. The higher the
charge pump current, the higher the PLL bandwidth.
Parameter Settings
The parameter settings to configure the bandwidth of the ALTPLL IP core are located on the Bandwidth/SS
page of the ALTPLL parameter editor.
The following figure shows the bandwidth configuration options on the Bandwidth/SS page.
Figure 14: Bandwidth Configuration Options
The following list describes the preset values that you can choose:
• Low—PLL with a low bandwidth has better jitter rejection but a slower lock time.
• High—PLL with a high bandwidth has a faster lock time but tracks more jitter.
• Medium—A medium bandwidth offers a balance between lock time and jitter rejection.
If you select Auto, the ALTPLL parameter editor chooses the best possible bandwidth values to achieve the
desired PLL settings. In some cases, you can get a bandwidth value outside the Low and High preset range.
To set the bandwidth manually, select Custom, and specify the value. The compiler attempts to achieve the
value that you specify, or the closest possible value to achieve your desired setting. You can check the
bandwidth value in the compilation report.
The table on the right in the Bandwidth/SS page shows the values of the charge pump current, loop filter
resistance and capacitance, and the M counter.
An advanced level of control is also possible for precise control of the PLL loop filter characteristics. This
level allows you to select the charge pump current, and loop filter resistance and capacitance values explicitly.
The advanced parameters are:
charge_pump_current
,
loop_filter_r
, and
loop_filter_c
.
You can use the programmable bandwidth feature with the clock switchover or spread-spectrum features
to get the PLL output settings that you desire. You must set the bandwidth to Auto if you want to enable
the spread-spectrum feature.
These parameter settings create no additional top-level ports.
Summary of Programmable Bandwidth Support
The following table summarizes programmable bandwidth support in the different device families.
Altera Corporation ALTPLL (Phase-Locked Loop) IP Core User Guide
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21 Parameter Settings
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2014.08.18