Altera ALTPLL (Phase-Locked Loop) IP Core - Manual (Page 45)

Description Condition Port Name
(7)
The data output for the serial scan
chain. You can use the
scandataout port to determine
when PLL reconfiguration is
completed. The last output is
cleared when reconfiguration
completes. Not available for
Cyclone and Cyclone II devices.
Optional
scandataout
This output port indicates that the
scan chain write operation is
initiated. The
scandone port goes
high when the scan chain write
operation initiates, and goes low
when the scan chain write
operation completes. Not available
for Cyclone, Cyclone II, Stratix,
and Stratix GX devices.
Optional
scandone
Serial clock output port.
This port is available only when
the PLL is in LVDS mode. Only
available for Arria GX, HardCopy
II, Stratix II, and Stratix II GX
devices.
Optional
sclkout[]
This output port indicates that the
VCO frequency has exceeded the
legal VCO range. Optional
vcounverrange
This output port indicates that the
VCO frequency has not met the
legal VCO range. Optional
vcounderrange
(7) Replace the brackets, [] , in the port name with an integer to get the exact name (for example, c0 , c1 , c3 , e0 ,
e1
,
e2
,
enable1
and
sclkout0
).
Altera Corporation ALTPLL (Phase-Locked Loop) IP Core User Guide
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45 ALTPLL Output Ports
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2014.08.18