Upgrading ip cores, Figure 25: simulation in quartus ii design flow, Simulating altera designs – Altera ALTPLL (Phase-Locked Loop) IP Core User Manual

Upgrading ip cores, Figure 25: simulation in quartus ii design flow, Simulating altera designs | As <my_variant | Altera ALTPLL (Phase-Locked Loop) IP Core User Manual | Page 34 / 69