Altera Quartus II Scripting User Manual
Quartus ii scripting reference manual
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Table of contents
Document Outline
- Quartus II Scripting Reference Manual
- Contents
- About this Reference Manual
- 1. Introduction to the Quartus II Scripting Reference Manual
- 2. Command-line Executables
- quartus_asm
- quartus_cdb
- Usage
- --back_annotate=<demotion type>
- --bottom_up_scripts_output_directory[=<value>]
- --bottom_up_scripts_virtual_input_pin_delay[=<value>]
- --bottom_up_scripts_virtual_output_pin_delay[=<value>]
- --create_companion[=<companion revision>]
- --disable_auto_global_promotion_in_bottom_up_scripts[=on|off]
- --export_database=<directory>
- --generate_bottom_up_scripts[=on|off]
- --generate_hc_files
- --generate_hc_pll_delay
- --hc_archive[=<output file>]
- --hc_min_archive
- --hc_ready
- --hc_review
- --import_database=<directory>
- --include_all_logiclock_regions_in_bottom_up_scripts[=on|off]
- --include_design_partitions_in_bottom_up_scripts[=on|off]
- --include_global_signal_promotion_in_bottom_up_scripts[=on|off]
- --include_logiclock_regions_in_bottom_up_scripts[=on|off]
- --include_makefiles_with_bottom_up_scripts[=on|off]
- --include_pin_locations_in_bottom_up_scripts[=on|off]
- --include_project_creation_in_bottom_up_scripts[=on|off]
- --include_timing_assignments_in_bottom_up_scripts[=on|off]
- --include_virtual_input_pin_timing_in_bottom_up_scripts[=on|off]
- --include_virtual_output_pin_timing_in_bottom_up_scripts[=on|off]
- --include_virtual_pin_locations_in_bottom_up_scripts[=on|off]
- --include_virtual_pins_in_bottom_up_scripts[=on|off]
- --incremental_compilation_export[=<.qxp file>]
- --incremental_compilation_export_netlist_type=<POST_SYNTH|POST_FIT>
- --incremental_compilation_export_partition_name[=<name>]
- --incremental_compilation_export_routing[=on|off]
- --incremental_compilation_import[=on|off]
- --merge[=on|off]
- --mif_dependency=<mif_check>
- --netlist_type=<map|cmp|asm>
- --override_partition_netlist_type=<value>
- --post_map[=on|off]
- --remove_existing_regions_in_bottom_up_scripts[=on|off]
- --update_mif
- --vqm[=<.vqm file>]
- --write_eqn_file[=<.eqn file>]
- --write_rcf_for_vqm[=on|off]
- quartus_cpf
- Usage
- -a=<hexadecimal number>
- -c
- -d=<device name>
- -g=<voltage>
- -k=<filename and key id>
- -m=<PS|AP|FPP|PPA|PPS>
- -n=<pb|v|p>
- -o=<filename>
- -q=<frequency with units>
- -s=<device name>
- -u=<up|down>
- -w
- --configuration_mode=<PS|AP|FPP|PPA|PPS>
- --convert
- --count_dir=<up|down>
- --device=<device name>
- --frequency=<frequency with units>
- --key=<filename and key id>
- --operation=<pb|v|p>
- --option=<filename>
- --sfl_device=<device name>
- --start_address=<hexadecimal number>
- --voltage=<voltage>
- --write
- design_security
- hexout
- isc
- jam
- jbc
- jic
- pof
- rbf
- rpd
- svf
- ttf
- quartus_drc
- quartus_eda
- Usage
- --board_boundary_scan[=on|off]
- --board_signal_integrity[=on|off]
- --board_symbol[=on|off]
- --board_timing[=on|off]
- --formal_verification[=on|off]
- --format=<NONE>
- --gen_script=<NONE>
- --gen_testbench
- --glitch_filtering[=on|off]
- --output_directory=<NONE>
- --resynthesis[=on|off]
- --simulation[=on|off]
- --timing_analysis[=on|off]
- --tool=<3rd-party eda tool>
- --user_compiled_simlib_dir=<NONE>
- --vcd_tb_design_instance_name=<NONE>
- --vcd_type=<NONE>
- quartus_fit
- Usage
- --check_ios
- --check_netlist
- --early_timing_estimate[=<realistic|optimistic|pessimistic>]
- --effort=<standard|fast|auto>
- --fmax=<time unit>
- --incremental_signaltap
- --inner_num=<value>
- --io_smart_recompile
- --one_fit_attempt[=on|off]
- --optimize_io_register_for_timing[=on|off]
- --pack_register=<off|normal|minimize_area|minimize_area_with_chains|auto>
- --part=<device part>
- --seed=<value>
- --signalprobe
- --tco=<time unit>
- --tdc[=on|off]
- --tpd=<time unit>
- --tsu=<time unit>
- quartus_jbcc
- quartus_jli
- Usage
- -a=<action to perform>
- -c=<jtagserver cable number>
- -d=<procedure to disable>
- -e=<procedure to enable>
- -i
- -j
- -l
- -n
- --action=<action to perform>
- --cable=<jtagserver cable number>
- --disable=<procedure to disable>
- --dont_reset_jtag
- --enable=<procedure to enable>
- --enumerate_hardware
- --info
- --loquacious
- quartus_map
- Usage
- -l=<path>
- --analysis_and_elaboration
- --analyze_file=<design file>
- --convert_bdf_to_verilog=<.bdf file>
- --convert_bdf_to_vhdl=<.bdf file>
- --effort=<auto|fast>
- --enable_wysiwyg_resynthesis[=on|off]
- --family=<device family>
- --generate_cmp_file=<design file>
- --generate_functional_sim_netlist
- --generate_inc_file=<design file>
- --generate_inst_file=<design file>
- --generate_symbol=<design file>
- --ignore_carry_buffers[=on|off]
- --ignore_cascade_buffers[=on|off]
- --incremental_compilation=<off|full_incremental_compilation>
- --lib_path=<path>
- --optimize=<area|speed|balanced>
- --parallel[=on|off]
- --part=<device>
- --partition=<NONE>
- --source=<source file>
- --state_machine_encoding=<auto|minimal_bits|one_hot|user_encoded>
- --update_wysiwyg_parameters
- --verilog_macro=<NONE>
- quartus_pgm
- quartus_pow
- Usage
- --default_input_io_toggle_rate=<toggle rate value>
- --default_toggle_rate=<toggle rate value>
- --estimate_power[=on|off]
- --input_saf[=<SAF Filename>]
- --input_vcd[=<VCD Filename>]
- --no_input_file
- --output_epe=<EPE Filename>
- --output_saf=<SAF Filename>
- --use_vectorless_estimation[=on|off]
- --vcd_filter_glitches[=on|off]
- --voltage=<value_in_mV>
- quartus_sh
- quartus_si
- quartus_sim
- Usage
- -c=<revision name>
- --cell_delay_model_type=<transport|inertial>
- --check_outputs[=on|off]
- --interconnect_delay_model_type=<transport|inertial>
- --memory_limiter[=on|off]
- --mode=<functional|timing|timing_using_fast_timing_model>
- --overwrite_waveform[=on|off]
- --perform_glitch_filtering=<auto|always|never>
- --power_vcd_output=<target file>
- --pvt_multicorner[=on|off]
- --pvt_temperature=<value_in_C>
- --pvt_timing_model_type=<slow|fast>
- --pvt_voltage=<value_in_mV>
- --rev=<revision name>
- --saf_output=<target file>
- --simulation_results_format=<VWF|CVWF|VCD>
- --vector_comparison_rule_value_0=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_comparison_rule_value_1=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_comparison_rule_value_dc=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_comparison_rule_value_h=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_comparison_rule_value_l=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_comparison_rule_value_u=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_comparison_rule_value_w=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_comparison_rule_value_x=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_comparison_rule_value_z=<0,1,X,L,H,W,Z,U and/or DC>
- --vector_source=<vector source file>
- quartus_sta
- quartus_stp
- quartus_tan
- Usage
- --check_constraints[=<setup|hold|both>]
- --combined_model[=on|off]
- --create_timing_netlist
- --datasheet[=<output file name>]
- --delay_annotation_only
- --do_min_analysis[=on|off]
- --dump_atom_generated_clocks
- --fast_model[=on|off]
- --fmax=<time unit>
- --post_map
- --speed=<device speed grade>
- --tao[=<.tao file>]
- --tao_summary
- --tco=<time unit>
- --th=<time unit>
- --timing_analysis_only
- --tpd=<time unit>
- --tristate
- --tsu=<time unit>
- --zero_ic_delays
- Common Options
- Compiler Options
- Parallel Processing Options
- Settings File Options
- Tcl Options
- 3. Tcl Packages & Commands
- advanced_timing
- create_p2p_delays
- get_clock_delay_path
- get_delay_path
- get_delays_from_clocks
- get_delays_from_keepers
- get_illegal_delay_value
- get_max_delay_value
- get_timing_edge_delay
- get_timing_edge_info
- get_timing_edges
- get_timing_node_fanin
- get_timing_node_fanout
- get_timing_node_info
- get_timing_nodes
- is_legal_delay_value
- p2p_timing_cut_exist
- backannotate
- chip_planner
- add_new_cell
- add_new_io
- add_usage
- apply_command
- check_netlist_and_save
- check_node
- close_chip_planner
- connect_chain
- convert_signal_probes
- create_migrated_script
- delete_sp
- design_has_ace_support
- design_has_encrypted_ip
- disable_sp
- discard_all_changes
- discard_node_changes
- enable_sp
- export_stack_to
- get_info_parameters
- get_iports
- get_node_by_name
- get_node_info
- get_node_loc
- get_nodes
- get_oports
- get_port_by_type
- get_port_info
- get_sp_pin_list
- get_stack
- get_tile_power_setting
- list_sps
- make_ape_connection
- make_input_port
- make_output_port
- make_sp
- read_netlist
- remove_ape_connection
- remove_chain
- remove_input_port
- remove_old_cell
- remove_output_port
- remove_usage
- routing_path
- set_batch_mode
- set_node_info
- set_port_info
- set_tile_power_setting
- undo_command
- update_node_loc
- database_manager
- device
- flow
- incremental_compilation
- auto_partition_design
- create_partition
- delete_all_logiclock
- delete_all_partitions
- delete_logiclock
- delete_partition
- export_partition
- get_logiclock
- get_logiclock_contents
- get_partition
- get_partition_file_list
- import_partition
- partition_netlist_exists
- set_logiclock
- set_logiclock_contents
- set_partition
- insystem_memory_edit
- insystem_source_probe
- iptclgen
- jtag
- logic_analyzer_interface
- misc
- project
- assignment_group
- create_revision
- delete_revision
- execute_assignment_batch
- export_assignments
- get_all_assignment_names
- get_all_assignments
- get_all_global_assignments
- get_all_instance_assignments
- get_all_parameters
- get_all_quartus_defaults
- get_all_user_option_names
- get_assignment_info
- get_assignment_name_info
- get_current_revision
- get_global_assignment
- get_instance_assignment
- get_location_assignment
- get_name_info
- get_names
- get_parameter
- get_project_directory
- get_project_revisions
- get_top_level_entity
- get_user_option
- is_project_open
- project_archive
- project_close
- project_exists
- project_new
- project_open
- project_restore
- remove_all_global_assignments
- remove_all_instance_assignments
- remove_all_parameters
- resolve_file_path
- revision_exists
- set_current_revision
- set_global_assignment
- set_instance_assignment
- set_io_assignment
- set_location_assignment
- set_parameter
- set_power_file_assignment
- set_user_option
- test_assignment_trait
- report
- add_row_to_table
- create_report_panel
- delete_report_panel
- get_fitter_resource_usage
- get_number_of_columns
- get_number_of_rows
- get_report_panel_column_index
- get_report_panel_data
- get_report_panel_id
- get_report_panel_names
- get_report_panel_row
- get_report_panel_row_index
- get_timing_analysis_summary_results
- load_report
- read_xml_report
- save_report_database
- unload_report
- write_report_panel
- write_xml_report
- rtl
- sdc
- all_clocks
- all_inputs
- all_outputs
- all_registers
- create_clock
- create_generated_clock
- derive_clocks
- get_cells
- get_clocks
- get_nets
- get_pins
- get_ports
- remove_clock_groups
- remove_clock_latency
- remove_clock_uncertainty
- remove_disable_timing
- remove_input_delay
- remove_output_delay
- reset_design
- set_clock_groups
- set_clock_latency
- set_clock_uncertainty
- set_disable_timing
- set_false_path
- set_input_delay
- set_input_transition
- set_max_delay
- set_min_delay
- set_multicycle_path
- set_output_delay
- sdc_ext
- derive_clock_uncertainty
- derive_pll_clocks
- get_assignment_groups
- get_fanins
- get_fanouts
- get_keepers
- get_nodes
- get_partitions
- get_registers
- remove_annotated_delay
- remove_clock
- reset_timing_derate
- set_active_clocks
- set_annotated_delay
- set_max_skew
- set_net_delay
- set_scc_mode
- set_time_format
- set_timing_derate
- simulator
- compare_vector
- convert_vector
- create_simulation_breakpoint
- delete_all_simulation_breakpoint
- delete_simulation_breakpoint
- disable_all_simulation_breakpoint
- disable_simulation_breakpoint
- enable_all_simulation_breakpoint
- enable_simulation_breakpoint
- fast_write_to_simulation_memory
- force_simulation_value
- get_simulation_memory_info
- get_simulation_time
- get_simulation_value
- group_simulation_signal
- initialize_simulation
- partition_vector
- read_from_simulation_memory
- release_simulation_value
- run_simulation
- set_simulation_clock
- write_to_simulation_memory
- sta
- add_to_collection
- check_timing
- create_report_histogram
- create_slack_histogram
- create_timing_netlist
- create_timing_summary
- delete_timing_netlist
- enable_ccpp_removal
- enable_sdc_extension_collections
- get_available_operating_conditions
- get_cell_info
- get_clock_domain_info
- get_clock_fmax_info
- get_clock_info
- get_datasheet
- get_default_sdc_file_names
- get_edge_info
- get_edge_slacks
- get_min_pulse_width
- get_net_info
- get_node_info
- get_object_info
- get_operating_conditions
- get_operating_conditions_info
- get_partition_info
- get_path
- get_path_info
- get_pin_info
- get_point_info
- get_port_info
- get_register_info
- get_timing_paths
- locate
- query_collection
- read_sdc
- remove_from_collection
- report_advanced_io_timing
- report_bottleneck
- report_clock_fmax_summary
- report_clock_transfers
- report_clocks
- report_datasheet
- report_ddr
- report_exceptions
- report_max_skew
- report_metastability
- report_min_pulse_width
- report_net_delay
- report_net_timing
- report_partitions
- report_path
- report_rskm
- report_sdc
- report_skew
- report_tccs
- report_timing
- report_ucp
- set_operating_conditions
- timing_netlist_exist
- update_timing_netlist
- use_timequest_style_escaping
- write_sdc
- stp
- timing
- timing_assignment
- timing_report
- advanced_timing