Document Outline

• Contents
  • FIGURES
  • TABLES
• Board Description and Memory Maps
• Introduction
• Overview
• Requirements
• Block Diagrams
• Functional Description
  • No-VMEbus-Interface Option
  • VMEbus Interface and VMEchip2
• Memory Maps
  • Local Bus Memory Map
    • Normal Address Range
    • Detailed I/O Memory Maps
    • BBRAM/TOD Clock Memory Map
    • Interrupt Acknowledge Map
  • VMEbus Memory Map
    • VMEbus Accesses to the Local Bus
    • VMEbus Short I/O Memory Map
• Software Support Considerations
  • Interrupts
  • Cache Coherency
  • Sources of Local BERR*
    • Local Bus Time-out
    • VMEbus Access Time-out
    • VMEbus BERR*
    • Local DRAM Parity Error
    • VMEchip2
    • Bus Error Processing
  • Description of Error Conditions on the MVME172
    • MPU Parity Error
    • MPU Off-board Error
    • MPU TEA  Cause Unidentified
    • MPU Local Bus Time-out
    • DMAC VMEbus Error
    • DMAC Parity Error
    • DMAC Off-board Error
    • DMAC LTO Error
    • DMAC TEA  Cause Unidentified
    • LAN Parity Error
    • LAN Off-Board Error
    • LAN LTO Error
    • SCSI Parity Error
    • SCSI Off-Board Error
    • SCSI LTO Error
  • Example of the Proper Use of Bus Timers
  • MVME172 MC68060 Indivisible Cycles
  • Illegal Access to IP Modules from External VMEbus Masters
• VMEchip2
• Introduction
  • Summary of Major Features
• Functional Blocks
  • Local Bus to VMEbus Interface
    • Local Bus to VMEbus Requester
  • VMEbus to Local Bus Interface
  • Local Bus to VMEbus DMA Controller
    • No Address Increment DMA Transfers
    • DMAC VMEbus Requester
  • Tick and Watchdog Timers
    • Prescaler
    • Tick Timers
    • Watchdog Timer
  • VMEbus Interrupter
  • VMEbus System Controller
    • Arbiter
    • IACK Daisy-Chain Driver
    • Bus Timer
    • Reset Driver
  • Local Bus Interrupter and Interrupt Handler
  • Global Control and Status Registers
• LCSR Programming Model
  • Programming the VMEbus Slave Map Decoders
    • VMEbus Slave Ending Address Register 1
    • VMEbus Slave Starting Address Register 1
    • VMEbus Slave Ending Address Register 2
    • VMEbus Slave Starting Address Register 2
    • VMEbus Slave Address Translation Address Offset Register 1
    • VMEbus Slave Address Translation Select Register 1
    • VMEbus Slave Address Translation Address Offset Register 2
    • VMEbus Slave Address Translation Select Register 2
    • VMEbus Slave Write Post and Snoop Control Register 2
    • VMEbus Slave Address Modifier Select Register 2
    • VMEbus Slave Write Post and Snoop Control Register 1
    • VMEbus Slave Address Modifier Select Register 1
  • Programming the Local Bus to VMEbus Map Decoders
    • Local Bus Slave (VMEbus Master) Ending Address Register 1
    • Local Bus Slave (VMEbus Master) Starting Address Register 1
    • Local Bus Slave (VMEbus Master) Ending Address Register 2
    • Local Bus Slave (VMEbus Master) Starting Address Register 2
    • Local Bus Slave (VMEbus Master) Ending Address Register 3
    • Local Bus Slave (VMEbus Master) Starting Address Register 3
    • Local Bus Slave (VMEbus Master) Ending Address Register 4
    • Local Bus Slave (VMEbus Master) Starting Address Register 4
    • Local Bus Slave (VMEbus Master) Address Translation Address Register 4
    • Local Bus Slave (VMEbus Master) Address Translation Select Register 4
    • Local Bus Slave (VMEbus Master) Attribute Register 4
    • Local Bus Slave (VMEbus Master) Attribute Register 3
    • Local Bus Slave (VMEbus Master) Attribute Register 2
    • Local Bus Slave (VMEbus Master) Attribute Register 1
    • VMEbus Slave GCSR Group Address Register
    • VMEbus Slave GCSR Board Address Register
    • Local Bus to VMEbus Enable Control Register
    • Local Bus to VMEbus I/O Control Register
    • ROM Control Register
  • Programming the VMEchip2 DMA Controller
    • DMAC Registers
    • PROM Decoder, SRAM and DMA Control Register
    • Local Bus to VMEbus Requester Control Register
    • DMAC Control Register 1 (bits 07)
    • DMAC Control Register 2 (bits 815)
    • DMAC Control Register 2 (bits 07)
    • DMAC Local Bus Address Counter
    • DMAC VMEbus Address Counter
    • DMAC Byte Counter
    • Table Address Counter
    • VMEbus Interrupter Control Register
    • VMEbus Interrupter Vector Register
    • MPU Status and DMA Interrupt Count Register
    • DMAC Status Register
  • Programming the Tick and Watchdog Timers
    • VMEbus Arbiter Time-out Control Register
    • DMAC Ton/Toff Timers and VMEbus Global Time-out Control Register
    • VME Access, Local Bus, and Watchdog Time-out Control Register
    • Prescaler Control Register
    • Tick Timer 1 Compare Register
    • Tick Timer 1 Counter
    • Tick Timer 2 Compare Register
    • Tick Timer 2 Counter
    • Board Control Register
    • Watchdog Timer Control Register
    • Tick Timer 2 Control Register
    • Tick Timer 1 Control Register
    • Prescaler Counter
  • Programming the Local Bus Interrupter
    • Local Bus Interrupter Status Register (bits 2431)
    • Local Bus Interrupter Status Register (bits 1623)
    • Local Bus Interrupter Status Register (bits 815)
    • Local Bus Interrupter Status Register (bits 07)
    • Local Bus Interrupter Enable Register (bits 2431)
    • Local Bus Interrupter Enable Register (bits 1623)
    • Local Bus Interrupter Enable Register (bits 815)
    • Local Bus Interrupter Enable Register (bits 07)
    • Software Interrupt Set Register (bits 815)
    • Interrupt Clear Register (bits 2431)
    • Interrupt Clear Register (bits 1623)
    • Interrupt Clear Register (bits 815)
    • Interrupt Level Register 1 (bits 2431)
    • Interrupt Level Register 1 (bits 1623)
    • Interrupt Level Register 1 (bits 815)
    • Interrupt Level Register 1 (bits 07)
    • Interrupt Level Register 2 (bits 2431)
    • Interrupt Level Register 2 (bits 1623)
    • Interrupt Level Register 2 (bits 815)
    • Interrupt Level Register 2 (bits 07)
    • Interrupt Level Register 3 (bits 2431)
    • Interrupt Level Register 3 (bits 1623)
    • Interrupt Level Register 3 (bits 815)
    • Interrupt Level Register 3 (bits 07)
    • Interrupt Level Register 4 (bits 2431)
    • Interrupt Level Register 4 (bits 1623)
    • Interrupt Level Register 4 (bits 815)
    • Interrupt Level Register 4 (bits 07)
    • Vector Base Register
    • I/O Control Register 1
    • I/O Control Register 2
    • I/O Control Register 3
    • Miscellaneous Control Register
• GCSR Programming Model
  • Programming the GCSR
    • VMEchip2 Revision Register
    • VMEchip2 ID Register
    • VMEchip2 LM/SIG Register
    • VMEchip2 Board Status/Control Register
    • General Purpose Register 0
    • General Purpose Register 1
    • General Purpose Register 2
    • General Purpose Register 3
    • General Purpose Register 4
    • General Purpose Register 5
• MC2 Chip
• Introduction
  • Summary of Major Features
• Functional Description
  • MC2 Chip Initialization
  • Flash and PROM Interface
  • BBRAM Interface
  • 82596CA LAN Interface
    • MPU Port and MPU Channel Attention
    • MC68060-Bus Master Support for 82596CA
    • LANC Bus Error
    • LANC Interrupt
  • 53C710 SCSI Controller Interface
  • SRAM Memory Controller
  • NON-ECC DRAM Memory Controller
  • Z85230 SCC Interface
  • Tick Timers
  • Watchdog Timer
  • Local Bus Timer
• Memory Map of the MC2 Chip Registers
• Programming Model
  • MC2 Chip ID Register
  • MC2 Chip Revision Register
  • General Control Register
  • Interrupt Vector Base Register
  • Programming the Tick Timers
    • Tick Timer 1 and 2 Compare and Counter Registers
    • LSB Prescaler Count Register
    • Prescaler Clock Adjust Register
    • Tick Timer 1 and 2 Control Registers
    • Tick Timer Interrupt Control Registers
  • DRAM Parity Error Interrupt Control Register
  • SCC Interrupt Control Register
  • Tick Timer 3 and 4 Control Registers
  • DRAM and SRAM Memory Controller Registers
    • DRAM Space Base Address Register
    • SRAM Space Base Address Register
    • DRAM Space Size Register
    • DRAM/SRAM Options Register
    • SRAM Space Size Register
  • LANC Error Status Register
  • 82596CA LANC Interrupt Control Register
  • LANC Bus Error Interrupt Control Register
  • SCSI Error Status Register
  • General Purpose Inputs Register
  • MVME172 Version Register
  • SCSI Interrupt Control Register
  • Tick Timer 3 and 4 Compare and Counter Registers
  • Bus Clock Register
  • PROM Access Time Control Register
  • Flash Access Time Control Register
  • ABORT Switch Interrupt Control Register
  • RESET Switch Control Register
  • Watchdog Timer Control Register
  • Access and Watchdog Time Base Select Register
  • DRAM Control Register
  • MPU Status Register
  • 32-bit Prescaler Count Register
• IP2 Chip
• Introduction
  • Summary of Major Features
• Functional Description
  • General Description
  • Cache Coherency
  • Local Bus to IndustryPack DMA Controllers
  • Clocking Environments and Performance
  • Programmable Clock
  • Error Reporting
    • Error Reporting as a Local Bus Slave
    • Error Reporting as a Local Bus Master
    • IndustryPack Error Reporting
  • Interrupts
• Overall Memory Map
• Programming Model
  • Chip ID Register
  • Chip Revision Register
  • Vector Base Register
  • IP_a, IP_b, IP_c, IP_d Memory Base Address Registers
    • IP_a or Double Size IP_ab Memory Base Address Registers
    • IP_b Memory Base Address Registers
    • IP_c or Double Size IP_cd Memory Base Address Registers
    • IP_d Memory Base Address Registers
  • IP_a, IP_b, IP_c, IP_d Memory Size Registers
  • IP_a, IP_b, IP_c, and IP_d; IRQ0 and IRQ1 Interrupt Control Registers
  • IP_a, IP_b, IP_c, and IP_d; General Control Registers
  • IP Clock Register
  • DMA Arbitration Control Register
  • IP RESET Register
  • Programming the DMA Controllers
    • DMA Enable Function
    • DMA Control and Status Register Set Definition
    • Programming the Programmable Clock
• Local Bus to IndustryPack Addressing
  • 8-Bit Memory Space
  • 16-Bit Memory Space
  • 32-Bit Memory Space
  • IP_a I/O Space
  • IP_ab I/O Space
  • IP_a ID Space
• IP to Local Bus Data Routing
  • Memory Space Accesses
  • I/O and ID Space Accesses
• MCECC
• Introduction
• Features
• Functional Description
  • General Description
  • Performance
  • Cache Coherency
  • ECC
    • Cycle Types
    • Error Reporting
    • Single Bit Error (Cycle Type = Burst Read or Non-Burst Read)
    • Double Bit Error (Cycle Type = Burst Read or Non-Burst Read)
    • Triple (or Greater) Bit Error (Cycle Type = Burst Read or Non-Burst Read)
    • Cycle Type = Burst Write
    • Single Bit Error (Cycle Type = Non-Burst Write)
    • Double Bit Error (Cycle Type = Non-Burst Write)
    • Triple (or Greater) Bit Error (Cycle Type = Non-Burst Write)
    • Single Bit Error (Cycle Type = Scrub)
    • Double Bit Error (Cycle Type = Scrub)
    • Triple (or Greater) Bit Error (Cycle Type = Scrub)
  • Error Logging
  • Scrub
  • Refresh
  • Arbitration
  • Chip Defaults
• Programming Model
  • Chip ID Register
  • Chip Revision Register
  • Memory Configuration Register
  • Dummy Register 0
  • Dummy Register 1
  • Base Address Register
  • DRAM Control Register
  • BCLK Frequency Register
  • Data Control Register
  • Scrub Control Register
  • Scrub Period Register Bits 15-8
  • Scrub Period Register Bits 7-0
  • Chip Prescaler Counter
  • Scrub Time On/Time Off Register
  • Scrub Prescaler Counter (Bits 21-16)
  • Scrub Prescaler Counter (Bits 15-8)
  • Scrub Prescaler Counter (Bits 7-0)
  • Scrub Timer Counter (Bits 15-8)
  • Scrub Timer Counter (Bits 7-0)
  • Scrub Address Counter (Bits 26-24)
  • Scrub Address Counter (Bits 23-16)
  • Scrub Address Counter (Bits 15-8)
  • Scrub Address Counter (Bits 7-4)
  • Error Logger Register
  • Error Address (Bits 31-24)
  • Error Address (Bits 23-16)
  • Error Address Bits (15-8)
  • Error Address Bits (7-4)
  • Error Syndrome Register
  • Defaults Register 1
  • Defaults Register 2
  • Initialization
• Syndrome Decode
• Related Documentation
• Motorola Computer Group Documents
  • Literature Updates
• Manufacturers’ Documents
• Using Interrupts on the MVME172
• Introduction
• VMEchip2 Tick Timer 1 Periodic Interrupt Example
• Index