Document Outline

• Contents
• List of Figures
• List of Tables
• About This Manual
  • Summary of Changes
  • Overview of Contents
  • Comments and Suggestions
  • Conventions Used in This Manual
• Board Description and Memory Maps
  • Introduction
  • Overview
  • Summary of Features
  • System Block Diagram
  • Functional Description
    • VMEbus Interface
    • Front Panel
    • PCI interface
      • P2 I/O
  • Programming Model
    • Processor Memory Maps
      • Default Processor Memory Map
      • Processor CHRP Memory Map
      • Processor PREP Memory Map
      • PCI Configuration Access
    • PCI Memory Maps
      • Default PCI Memory Map
      • PCI CHRP Memory Map
      • PCI PREP Memory Map
    • VMEbus Mapping
      • VMEbus Master Map
      • VMEbus Slave Map
    • Falcon-Controlled System Registers
      • System Configuration Register (SYSCR)
      • Memory Configuration Register (MEMCR)
      • System External Cache Control Register (SXCCR)
      • Processor 0 External Cache Control Register (P0XCCR)
      • Processor 1 External Cache Control Register (P1XCCR)
      • CPU Control Register
  • ISA Local Resource Bus
    • W83C553 PIB Registers
    • 16550 UART
    • General-Purpose Readable Jumpers
    • NVRAM/RTC and Watchdog Timer Registers
    • Module Configuration and Status Registers
      • CPU Configuration Register
      • Base Module Feature Register
      • Base Module Status Register (BMSR)
      • Seven-Segment Display Register
    • VME Registers
      • LM/SIG Control Register
      • LM/SIG Status Register
      • Location Monitor Upper Base Address Register
      • Location Monitor Lower Base Address Register
      • Semaphore Register 1
      • Semaphore Register 2
      • VME Geographical Address Register (VGAR)
    • Emulated Z8536 CIO Registers and Port Pins
      • Emulated Z8536 Registers
      • Z8536 CIO Port Pins
    • ISA DMA Channels
• Raven PCI Bridge ASIC
  • Introduction
  • Features
  • Block Diagram
  • Functional Description
    • MPC Bus Interface
      • MPC Address Mapping
      • MPC Slave
      • MPC Write Posting
      • MPC Master
      • MPC Arbiter
      • MPC Bus Timer
    • PCI Interface
      • PCI Address Mapping
      • PCI Slave
      • PCI Write Posting
      • PCI Master
      • Generating PCI Cycles
    • Endian Conversion
      • When MPC Devices are Big-Endian
      • When MPC Devices are Little-Endian
      • Raven Registers and Endian Mode
    • Error Handling
    • Transaction Ordering
  • Raven Registers
    • MPC Registers
      • Vendor ID/Device ID Registers
      • Revision ID Register
      • General Control-Status/Feature Registers
      • MPC Arbiter Control Register
      • Prescaler Adjust Register
      • MPC Error Enable Register
      • MPC Error Status Register
      • MPC Error Address Register
      • MPC Error Attribute Register - MERAT
      • PCI Interrupt Acknowledge Register
      • MPC Slave Address (0,1 and 2) Registers
      • MPC Slave Address (3) Register
      • MPC Slave Offset/Attribute (0,1 and 2) Registers
      • MPC Slave Offset/Attribute (3) Registers
      • General-Purpose Registers
    • PCI Registers
      • Vendor ID/ Device ID Registers
      • PCI Command/ Status Registers
      • Revision ID/ Class Code Registers
      • I/O Base Register
      • Memory Base Register
      • PCI Slave Address (0,1,2 and 3) Registers
      • PCI Slave Attribute/ Offset (0,1,2 and 3) Registers
      • CONFIG_ADDRESS Register
      • CONFIG_DATA Register
  • Raven Interrupt Controller
    • Features
    • Architecture
      • Readability of CSR
      • Interrupt Source Priority
      • Processor’s Current Task Priority
      • Nesting of Interrupt Events
      • Spurious Vector Generation
      • Interprocessor Interrupts (IPI)
      • 8259 Compatibility
      • Raven-Detected Errors
      • Timers
      • Interrupt Delivery Modes
    • Block Diagram Description
      • Program-Visible Registers
      • Interrupt Pending Register (IPR)
      • Interrupt Selector (IS)
      • Interrupt Request Register (IRR)
      • In-Service Register (ISR)
      • Interrupt Router
    • MPIC Registers
      • RavenMPIC Registers
      • Feature Reporting Register
      • Global Configuration Register
      • Vendor Identification Register
      • Processor Init Register
      • IPI Vector/Priority Registers
      • Spurious Vector Register
      • Timer Frequency Register
      • Timer Current Count Registers
      • Timer Base Count Registers
      • Timer Vector/Priority Registers
      • Timer Destination Registers
      • External Source Vector/Priority Registers
      • External Source Destination Registers
      • Raven-Detected Errors Vector/Priority Register
      • Raven-Detected Errors Destination Register
      • Interprocessor Interrupt Dispatch Registers
      • Interrupt Task Priority Registers
      • Interrupt Acknowledge Registers
      • End-of-Interrupt Registers
    • Programming Notes
      • External Interrupt Service
      • Reset State
      • Interprocessor Interrupts
      • Dynamically Changing I/O Interrupt Configuration
      • EOI Register
      • Interrupt Acknowledge Register
      • 8259 Mode
      • Current Task Priority Level
    • Architectural Notes
• Falcon ECC Memory Controller Chip Set
  • Introduction
  • Features
  • Block Diagrams
  • Functional Description
    • Bit Ordering Convention
    • Performance
      • Four-beat Reads/Writes
      • Single-beat Reads/Writes
      • DRAM Speeds
      • ROM/Flash Speeds
    • PowerPC 60x Bus Interface
      • Responding to Address Transfers
      • Completing Data Transfers
      • Cache Coherency
      • Cache Coherency Restrictions
      • L2 Cache Support
    • ECC
      • Cycle Types
      • Error Reporting
      • Error Logging
    • DRAM Tester
    • ROM/Flash Interface
    • Refresh/Scrub
      • Blocks A and/or B Present, Blocks C and D Not Present
      • Blocks A and/or B Present, Blocks C and/or D Present
    • DRAM Arbitration
    • Chip Defaults
    • External Register Set
    • CSR Accesses
  • Programming Model
    • CSR Architecture
    • Register Summary
    • Detailed Register Bit Descriptions
      • Vendor/Device Register
      • Revision ID/ General Control Register
      • DRAM Attributes Register
      • DRAM Base Register
      • CLK Frequency Register
      • ECC Control Register
      • Error Logger Register
      • Error Address Register
      • Scrub/Refresh Register
      • Refresh/Scrub Address Register
      • ROM A Base/Size Register
      • ROM B Base/Size Register
      • DRAM Tester Control Registers
      • 32-Bit Counter
      • Test SRAM
      • Power-Up Reset Status Register 1
      • Power-Up Reset Status Register 2
      • External Register Set
  • Software Considerations
    • Parity Checking on the PowerPC Bus
    • Programming ROM/Flash Devices
    • Writing to the Control Registers
    • Sizing DRAM
    • ECC Codes
    • Data Paths
• Universe (VMEbus to PCI) Chip
  • Introduction
  • Features
  • Block Diagram
  • Functional Description
    • VMEbus Interface
      • Universe as VMEbus Slave
      • Universe as VMEbus Master
    • PCI Bus Interface
      • Universe as PCI Slave
      • Universe as PCI Master
    • Interrupter
      • VMEbus Interrupt Handling
    • DMA Controller
    • Universe Control and Status Registers (UCSR)
      • Universe Register Map
    • Universe Chip Problems after PCI Reset
      • Description
      • Workarounds
    • Examples
      • Example 1: MVME2600 Series Board Exhibits PCI Reset Problem
      • Example 2: MVME3600 Series Board Acts Differently
      • Example 3: Universe Chip is Checked at Tundra
• Programming Details
  • Introduction
  • PCI Arbitration
  • Interrupt Handling
    • RavenMPIC
    • 8259 Interrupts
  • ISA DMA Channels
  • Exceptions
    • Sources of Reset
    • Soft Reset
    • Universe Chip Problems after PCI Reset
    • Error Notification and Handling
  • Endian Issues
    • Processor/Memory Domain
    • Role of the Raven ASIC
    • PCI Domain
      • PCI-SCSI
      • PCI/Ethernet
      • PCI-Graphics
    • Role of the Universe ASIC
    • VMEbus Domain
  • ROM/Flash Initialization
• Related Documentation
  • Motorola Computer Group Documents
  • Manufacturers’ Documents
  • Related Specifications
• Glossary
• Index