Altera ALTPLL (Phase-Locked Loop) IP Core User Manual
Altpll (phase-locked loop) ip core user guide, Altpll features, Phase-locked loop
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Table of contents
Document Outline
- ALTPLL (Phase-Locked Loop) IP Core User Guide
- ALTPLL Features
- Phase-Locked Loop
- Types of PLLs
- Operation Modes
- Output Clocks
- Advanced Features
- PLL Output Counter Cascading
- Installing and Licensing IP Cores
- Customizing and Generating IP Cores
- Simulating Altera IP Cores in other EDA Tools
- Upgrading IP Cores
- Migrating IP Cores to a Different Device
- Ports and Parameters
- Design Examples
- Document Revision History
- ALTPLL Features