Altera DisplayPort MegaCore Function - Manual (Page 134)

Bit Bit Name Function
2:0 CH_COUNT Channel count
• 000 = 1 channel
• 001 = 2 channels
...
• 111 = 8 channels
Source CRC Registers
The CRC registers are allocated at addresses:
• 0x0030 through 0×0032 for Stream 0
• 0x0050 through 0×0052 for Stream 1
• 0x0070 through 0×0072 for Stream 2
• 0x0090 through 0×0092 for Stream 3
Note: Only registers for Stream 0 are listed in the following sections.
Computed video CRC red component,
DPTX0_CRC_R
, bits.
Address: 0×0030
Direction: RO
Reset: 0×00000000
Table 9-26: DPTX0_CRC_R Bits
Bit Bit Name Function
31:16 Unused
15:0 CRC_R Input video CRC for the red
component
Computed video CRC green component,
DPTX0_CRC_G
, bits.
Address: 0×0031
Direction: RO
Reset: 0×00000000
Table 9-27: DPTX0_CRC_G Bits
Bit Bit Name Function
31:16 Unused
UG-01131
2015.05.04
Source CRC Registers 9-13
DisplayPort Source Register Map and DPCD Locations Altera Corporation
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