Altera DisplayPort MegaCore Function - Manual (Page 136)

Bit Bit Name Function
0
MST_EN Enable or disable MST
• 1 = MST framing
• 0 = SST framing
When you assert
VCPTAB_UPD_FORCE
, the source forces the VC payload table contained in
DPTX_MST_VCPTAB0
through
DPTX_MST_VCPTAB7
to be taken immediately into use. No ACT sequence is
generated in this case.
When you assert
VCPTAB_UPD_REQ
, the source requests to generate an ACT sequence and after that, use
the VC payload table contained in
DPTX_MST_VCPTAB0
through
DPTX_MST_VCPTAB7
.
DPTX_MST_VCPTAB0
VC Payload ID Table
Address: 0×00a2
Direction: RW
Reset: 0×00000000
Table 9-30: DPTX_MST_VCPTAB0 Bits
Bit Bit Name Function
31:28
VCPSLOT7 VC payload ID or slot 7
27:24
VCPSLOT6 VC payload ID or slot 6
23:20
VCPSLOT5 VC payload ID or slot 5
19:16
VCPSLOT4 VC payload ID or slot 4
15:12
VCPSLOT3 VC payload ID or slot 3
11:8
VCPSLOT2 VC payload ID or slot 2
7:4
VCPSLOT1 VC payload ID or slot 1
3:0 Reserved Reserved
DPTX_MST_VCPTAB1
VC Payload ID Table
Address: 0×00a3
Direction: RW
Reset: 0×00000000
UG-01131
2015.05.04
DPTX_MST_VCPTAB0 9-15
DisplayPort Source Register Map and DPCD Locations Altera Corporation
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