Altera DisplayPort MegaCore Function - Manual (Page 169)

Address: 0×00a2
Direction: RW
Reset: 0×00000000
Table 10-34: DPRX_MST_VCPTAB0 Bits
Bit Bit Name Function
31:28
VCPSLOT7 VC payload ID or slot 7
27:24
VCPSLOT6 VC payload ID or slot 6
23:20
VCPSLOT5 VC payload ID or slot 5
19:16
VCPSLOT4 VC payload ID or slot 4
15:12
VCPSLOT3 VC payload ID or slot 3
11:8
VCPSLOT2 VC payload ID or slot 2
7:4
VCPSLOT1 VC payload ID or slot 1
3:0 Reserved Reserved
DPRX_MST_VCPTAB1
VC Payload ID Table
Address: 0×00a3
Direction: RW
Reset: 0×00000000
Table 10-35: DPRX_MST_VCPTAB1 Bits
Bit Bit Name Function
31:28
VCPSLOT15 VC payload ID or slot 15
27:24
VCPSLOT14 VC payload ID or slot 14
23:20
VCPSLOT13 VC payload ID or slot 13
19:16
VCPSLOT12 VC payload ID or slot 12
15:12
VCPSLOT11 VC payload ID or slot 11
11:8
VCPSLOT10 VC payload ID or slot 10
7:4
VCPSLOT9 VC payload ID or slot 9
10-18 DPRX_MST_VCPTAB1
UG-01131
2015.05.04
Altera Corporation DisplayPort Sink Register Map and DPCD Locations
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