Altera DisplayPort MegaCore Function - Manual (Page 80)

HSMC Connector J4B
AUX_RX_DRV_OUT
Input
RX AUX channel output.
Use this signal if the external AUX driver/
receiver(U3) is populated.
TX_CAD
,
RX_SDA_DDC
,
RX_SCL_DDC
,
TX_SDA_DDC
,
TX_SCL_DDC
,
fPLL_CLK_
OUT2p
,
fPLL_CLK_OUT2n
Not used —
HSMC Connector J4C
AUX_TX_PC
,
AUX_TX_NC
I/O
TX AUX channel differential pair.
If the external AUX driver/receiver chip,
SN65MLVD200 (U4), is populated on Bitec card,
the FPGA device should not drive these differential
signals. To avoid bus contention, remove the on-
chip bidirectional buffer,
aux_buffer_tx
, in the
demonstration top module. Instead, the FPGA
device should use
AUX_TX_DRV_IN
,
AUX_TX_DRV_OE
,
and
AUX_TX_DRV_OUT
signals.
Note: The
tx_aux_in
and
tx_aux_out
signals are
inverted. If the external AUX driver/receiver chip is
used, undo the inversion.
AUX_TX_DRV_IN
Output
TX AUX channel input.
Use this signal if the external AUX driver/
receiver(U4) is populated.
AUX_TX_DRV_OE
Input
TX AUX channel output enable.
Use this signal if the external AUX driver/
receiver(U4) is populated.
AUX_TX_DRV_OUT
Input
TX AUX channel output.
Use this signal if the external AUX driver/
receiver(U4) is populated.
DP RX Connector J1
CONFIG1
Input Cable Adapter Detect for dual mode support.
CONFIG2
Not used —
RTN_PWR
Input Return signal for
DP_PWR
.
UG-01131
2015.05.04
Required Hardware 6-19
DisplayPort IP Core Hardware Demonstration Altera Corporation
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