Altera DisplayPort MegaCore Function - Manual (Page 185)

Location Name Address Without
Controller
With Controller
EDP_CONFIGURATION_CAP 0×000D — Yes
TRAINING_AUX_RD_INTERVAL 0×000E — Yes
ADAPTER_CAP 0×000F — Yes
FAUX_CAP 0×0020 — Yes
MST_CAP 0×0021 — Yes
NUMBER_OF_AUDIO_ENDPOINTS 0×0022 — Yes
GUID 0×0030 — Yes
DWN_STRM_PORTX_CAP 0×0080 Yes Yes
LINK_BW_SET 0×0100 Yes Yes
LANE_COUNT_SET 0×0101 Yes Yes
TRAINING_PATTERN_SET 0×0102 Yes Yes
TRAINING_LANE0_SET 0×0103 Yes Yes
TRAINING_LANE1_SET 0×0104 Yes Yes
TRAINING_LANE2_SET 0×0105 Yes Yes
TRAINING_LANE3_SET 0×0106 Yes Yes
DOWNSPREAD_CTRL 0×0107 Yes Yes
MAIN_LINK_CHANNEL_CODING_SET 0×0108 Yes Yes
I2C_SPEED_CONTROL 0×0109 — Yes
EDP_CONFIGURATION_SET 0×010A — Yes
LINK_QUAL_LANE0_SET 0×010B — Yes
LINK_QUAL_LANE1_SET 0×010C — Yes
LINK_QUAL_LANE2_SET 0×010D — Yes
LINK_QUAL_LANE3_SET 0×010E — Yes
10-34 Sink-Supported DPCD Locations
UG-01131
2015.05.04
Altera Corporation DisplayPort Sink Register Map and DPCD Locations
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