Altera DisplayPort MegaCore Function - Manual (Page 152)

DisplayPort Sink Register Map and DPCD
Locations
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DisplayPort sink instantiations greatly benefit from and may optionally use an embedded controller
(Nios II processor or another controller). This section describes the register map.
Table 10-1: Notation
Shorthand Definition
RW Read/write
RO Read only
WO Write only
CRO Clear on read or write, read only
CWO Clear on read or write, write only
Sink General Registers
This section describes the general registers.
DPRX_RX_CONTROL
The IRQ is asserted when
AUX_IRQ_EN
= 1 and in register
DPRX_AUX_CONTROL
the flag
MSG_READY
= 1. IRQ
is de-asserted by setting
AUX_IRQ_EN
to 0 or reading from
DPRX_AUX_COMMAND
.
RECONFIG_LINKRATE
drives
the
rx_reconfig_req
.
RX_LINK_RATE
drives
rx_link_rate
.
Address: 0×0000
Direction: RW
Reset: 0×00000000
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