Controller interface, Controller interface -11 – Altera DisplayPort MegaCore Function User Manual

Page 27

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Table 4-8: TX Transceiver Interface

n

is the number of TX lanes,

s

is the number of symbols per clock.

Note: Connect the DisplayPort signals to the Native PHY signals of the same name.

Interface

Port Type

Clock

Domain

Port

Direction

Description

TX transceiver

interface

Clock

N/A

tx_std_clkout[n–1:0]

Input

TX transceiver clock

out

Conduit

tx_std_

clkout

tx_parallel_

data[n*s*10–1:0]

Output Parallel data for TX

transceiver

Conduit

N/A

tx_pll_powerdown

Output PLL power down for

TX transceiver

Conduit

xcvr_mgmt_

clk

tx_digitalreset[n–

1:0]

Output Resets the digital TX

portion of TX

transceiver

Conduit

N/A

tx_analogreset[n–

1:0]

Output Resets the analog TX

portion of TX

transceiver

Conduit

N/A

tx_cal_busy[n–1:0]

Input

Calibration in

progress signal from

TX transceiver

Conduit

N/A

tx_pll_locked

Input

PLL locked signal

from TX transceiver

Controller Interface

The controller interface allows you to control the source from an external or on-chip controller, such as

the Nios II processor. The controller can control the DisplayPort link parameters and the AUX channel

controller.
The AUX channel controller interface works with a simple serial-port-type peripheral that operates in a

polled mode. Because the DisplayPort AUX protocol is a master-slave interface, the DisplayPort source

(the master) starts a transaction by sending a request and then waits for a reply from the attached sink.
The controller interface includes a single interrupt source. The interrupt notifies the controller of an HPD

signal state change. Your system can interrogate the

DP_TX_STATUS

register to determine the cause of the

interrupt. Writing to the

DP_TX_STATUS

register clears the pending interrupt event.

Related Information

Multiplexer

on page 4-4

DisplayPort Source Register Map and DPCD Locations

on page 9-1

DisplayPort source instantiations require an embedded controller (Nios II processor or another

controller) to act as the policy maker.

UG-01131

2015.05.04

Controller Interface

4-11

DisplayPort Source

Altera Corporation

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