Altera DisplayPort MegaCore Function - Manual (Page 192)

Date Version Changes
December 2014 2014.12.15
• Added information about multi-stream support (MST, 1 to 4 source
and sink streams). You can access this feature using these
parameters:
• Support MST
• Max stream count
• Added support for 4Kp60 resolution.
• Added information about clock recovery feature for the hardware
demonstration.
• Removed information for double reference clocks (162MHz and
270MHz) for transceiver clocking. The IP core no longer supports
double reference clocks.
• Added new source registers:
• 0×00a0 (
DPTX_MST_CONTROL1
)
• 0×00a2 (
DPTX _MST_VCPTAB0
)
• 0×00a3 (
DPTX _MST_VCPTAB
)
• 0×00a3 (
DPTX _MST_VCPTAB1
)
• 0×00a4 (
DPTX _MST_VCPTAB2
)
• 0×00a5 (
DPTX _MST_VCPTAB3
)
• 0×00a6 (
DPTX _MST_VCPTAB4
)
• 0×00a7 (
DPTX _MST_VCPTAB5
)
• 0×00a8 (
DPTX _MST_VCPTAB6
)
• 0×00a9 (
DPTX _MST_VCPTAB7
)
• 0×00aa (
DPTX _MST_TAVG_TS
)
• Added new sink registers:
• 0×0006 (
DPRX_BER_CNTI0
)
• 0×0007 (
DPRX_BER_CNTI1
)
• 0×00a0 (
DPRX_MST_CONTROL1
)
• 0×00a1 (
DPRX_MST_STATUS1
)
• 0×00a2 (
DPRX _MST_VCPTAB0
)
• 0×00a3 (
DPRX _MST_VCPTAB1
)
• 0×00a4 (
DPRX _MST_VCPTAB2
)
• 0×00a5 (
DPRX _MST_VCPTAB3
)
• 0×00a6 (
DPRX _MST_VCPTAB4
)
• 0×00a7 (
DPRX _MST_VCPTAB5
)
• 0×00a8 (
DPRX _MST_VCPTAB6
)
• 0×00a9 (
DPRX _MST_VCPTAB7
)
A-2 Document Revision History
UG-01131
2015.05.04
Altera Corporation Additional Information
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