Altera DisplayPort MegaCore Function - Manual (Page 29)

Figure 4-4: Video Input Data Format
18 bpp to 48 bpp port width when
txN_video_in
port width is 48 (16 bpc, 1 pixel per clock)
47 32 31 16 15 0 txN_vid_data[47:0]
18 bpp RGB
24 bpp RGB/YCBCr444 (8 bpc)
30 bpp RGB/YCBCr444 (10 bpc)
36 bpp RGB/YCBCr444 (12 bpc)
48 bpp RGB/YCBCr444 (16 bpc)
The following figure shows the sub-sampled 4:2:2 color format for a video port width of n. The most-
significant half of the video port always transfers the Y component while the least-significant half of the
video port transfers the alternate Cr or Cb component. If the Y/Cb/Cr component widths are less than
n/2, they must be most-significant bit aligned with respect to the n and n/2-1 boundaries.
Figure 4-5: Sub-Sampled 4:2:2 Color Format Video Port
n/2-1 0 n - 1 n/2 txN_vid_data[n - 1:0]
If you set the Pixel input mode option to Dual or Quad, the IP core sends two or four pixels in parallel,
respectively. To support video resolutions with horizontal active, front porch or back porch of a length
not divisible by 2 or 4, the following signals are widened:
• Horizontal and vertical syncs
• Data enable
The following figure shows the pixel data order from least significant bits to most significant bits.
Figure 4-6: Video Input Data Alignment
For RGB 18 bpp when
txN_video_in
port width is 96 (8 bpc, 4 pixels per clock)
71 48 47 24 23 0 txN_vid_data[95:0] 95 72
Pixel 3 Pixel 2 Pixel 1 Pixel 0
TX Transceiver Interface
The transceiver or Native PHY IP core instance is no longer instantiated within the DisplayPort IP core.
The DisplayPort IP uses a soft 8B/10B encoder. This interface provides TX encoded video data
(
tx_parallel_data
) in either dual symbol (20-bit) or quad symbol (40-bit) mode and drives the digital
UG-01131
2015.05.04
TX Transceiver Interface 4-13
DisplayPort Source Altera Corporation
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