Altera DisplayPort MegaCore Function - Manual (Page 96)

View the Results
You can view the results in the ModelSim GUI by loading various .do files in the Wave viewer.
1. Launch the ModelSim GUI with the vsim command.
2. In the ModelSim Tcl window, execute the dataset open command:
dataset open vsim.wlf
3. Select View > Open Wave files.
4. Load the .do files to view the waveforms (refer back to Table 7-1 for a listing of the files).
Figure 7-3: RX Reconfiguration Waveform
In the timing diagram below,
rx_link_rate
is set to 1 (HBR). When the core makes a request, the
rx_reconfig_req
port goes high. The user logic asserts
rx_reconfig_ack
and then reconfigures the
transceiver. During reconfiguration, the user logic holds
rx_reconfig_busy
high; the user logic drives
it low when reconfiguration completes.
xcvr_mgmt_clk
rx_link_rate
rx_reconfig_req
rx_reconfig_ack
rx_reconfig_busy
tx_link_rate
tx_vod
tx_emp
tx_analog_reconfig_req
tx_analog_reconfig_ack
tx_analog_reconfig_busy
tx_reconfig_req
tx_reconfig_ack
tx_reconfig_busy
reconfig_busy
reconfig_mgmt_address
reconfig_mgmt_write
reconfig_mgmt_writedata
reconfig_mgmt_waitrequest
reconfig_mgmt_read
reconfig_mgmt_readdata
7-8 View the Results
UG-01131
2015.05.04
Altera Corporation DisplayPort IP Core Simulation Example
Send Feedback