Altera DisplayPort MegaCore Function - Manual (Page 71)

Interface Port Type Clock Domain Port Direction Description
Video Output Conduit
rec_clk
rec_clk
Output Reconstructed video
clock.
rec_clk_x2
Output Reconstructed video
clock double frequency.
vidout
(BPP*PIXEL
S_PER_
CLOCK–1:0)
Output Pixel data.
hsync
Output Horizontal sync. This
signal can be active-high
or active-low depending
on the sync polarity from
MSA.
vsync
Output Vertical sync. This signal
can be active-high or
active-low depending on
the sync polarity from
MSA.
de
Output Data enable. This signal
is always active high.
field2
Output The clock recovery core
asserts this signal during
the second video field for
interlaced timings.
reset_out
Output The clock recovery core
asserts this signal when
the other video output
signals are not valid. This
signal is asynchronous.
Video Input Port
You must connect the clock recovery core video input port to the DisplayPort sink core video output
image port.
6-10 Video Input Port
UG-01131
2015.05.04
Altera Corporation DisplayPort IP Core Hardware Demonstration
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