Altera DisplayPort MegaCore Function - Manual (Page 97)

Figure 7-4: TX Reconfiguration Waveform
In the timing diagram below,
tx_link_rate
is set to 1 (HBR). When the core makes a request, the
tx_reconfig_req
port goes high. The user logic asserts
tx_reconfig_ack
and then reconfigures the
transceiver. During reconfiguration, the user logic holds
tx_reconfig_busy
high; the user logic drives
it low when reconfiguration completes.
xcvr_mgmt_clk
rx_link_rate
rx_reconfig_req
rx_reconfig_ack
rx_reconfig_busy
tx_link_rate
tx_reconfig_req
tx_reconfig_ack
tx_reconfig_busy
tx_vod
tx_emp
tx_analog_reconfig_req
tx_analog_reconfig_ack
tx_analog_reconfig_busy
reconfig_busy
reconfig_mgmt_address
reconfig_mgmt_write
reconfig_mgmt_writedata
reconfig_mgmt_waitrequest
reconfig_mgmt_read
reconfig_mgmt_readdata
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2015.05.04
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DisplayPort IP Core Simulation Example Altera Corporation
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